EPM3256AFC256-7 vs EPM3128AFC256-7N 对比

详细并排对比 EPM3256AFC256-7 出自 Altera 和 EPM3128AFC256-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3256AFC256-7 EPM3128AFC256-7N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $12.10 $19.85
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Macro Cells 256 128
Logic Array Blocks (LABs) 16 —
Usable Gates 10,000 2,500
User I/Os 161 98
Pin-to-Pin Logic Delay 4.5 ns (max) —
Counter Frequency 227.3 MHz (max) —
Propagation Delay (tpd) 10 ns —
Core Voltage 3.3 V —
I/O Compatibility 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) —
Process Technology CMOS EEPROM, 0.30 µm —
In-System Programmability IEEE Std. 1532-compliant 3.3-V ISP —
Boundary-Scan Test JTAG (IEEE 1149.1) —
封装 FBGA-256 (FineLine BGA), 256 balls 256-BGA (FineLine, FBGA)
工作温度 0 °C to 70 °C (Commercial) 0 C to +70 C (commercial)
Speed Grade -7 —
RoHS 状态 [DATA_NEEDED: RoHS compliance status] —
Architecture — CMOS EEPROM-based MAX
Propagation Delay (tPD) — 7.5 ns
Internal fMAX — 192.3 MHz
Supply Voltage - Core (VCCINT) — 3.3 V
Supply Voltage - I/O (VCCIO) — 3.3 V or 2.5 V
Logic Family — CMOS
Programmability — In-system (ISP), IEEE Std. 1532, JTAG (IEEE Std. 1149.1)
安装类型 — Surface Mount

数据手册与资源

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