EPM3256AQI208-10N vs EPM3256AQC208-10 对比

详细并排对比 EPM3256AQI208-10N 出自 Altera 和 EPM3256AQC208-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3256AQI208-10N EPM3256AQC208-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $9.75 $15.20
Family MAX 3000A MAX 3000A
Macrocells 256 256
User I/Os 161 161
Usable Gates 5,000 5,000
Logic Elements / LABs 16 Logic Array Blocks (LABs) —
Propagation Delay (tPD) 10 ns —
Counter Frequency 118.7 MHz (max, -10 speed grade) —
Speed Grade -10 —
Supply Voltage - Core 3.3 V —
I/O Logic Level Compatibility 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) —
工作温度 -40 C to +85 C (industrial) 0 °C to +70 °C (Commercial)
封装 208-pin PQFP (Plastic Quad Flat Pack) 208-BFQFP (PQFP, Gull Wing)
安装类型 Surface Mount Surface Mount
Programming Interface JTAG (IEEE 1149.1) ISP IEEE 1149.1 JTAG (ISP)
Process Technology CMOS EEPROM —
Hot-Socketing Support Yes —
RoHS 状态 Non-compliant (Pb-bearing PQFP package) [DATA_NEEDED: RoHS status]
Logic Family — CMOS (EEPROM-based)
引脚数 — 208
Pin-to-Pin Propagation Delay — 10 ns
Counter Frequency (max) — 227.3 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Tolerance — MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant
PCI-SIG Compliance — Yes (speed grades -4, -5, -6, -7, -10)
Global Clock Networks — 4 (CLK, CLR, OE, GCLK)

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