EPM3256ATC144-7 vs EPM3256ATI144-10 对比

详细并排对比 EPM3256ATC144-7 出自 Altera 和 EPM3256ATI144-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3256ATC144-7 EPM3256ATI144-10
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $17.06 $0.00
Family MAX 3000A —
Macrocells 256 —
User I/Os 116 —
Logic Elements / Gates 600 to 10,000 usable gates —
Propagation Delay (tPD) 7.5 ns —
Counter Frequency (fCNT) 227.3 MHz —
Speed Grade -7 —
Supply Voltage - Core (VCCINT) 3.3 V —
Supply Voltage - I/O (VCCIO) 2.5 V / 3.3 V / 5.0 V —
In-System Programming IEEE Std. 1532 compliant, 3.3 V ISP —
封装 TQFP-144 (LFQFP, gull-wing) 144-pin TQFP (20x20 mm)
工作温度 0C to +70C (Commercial) -40°C to +85°C (industrial)
引脚数量 144 —
安装类型 Surface Mount Surface Mount
PCI Compliance PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10) —
JTAG Support IEEE Std. 1149.1 boundary-scan —
Series — MAX 3000A
Programmable Type — In-System Programmable (ISP), EEPROM-based
Number of Macrocells — 256
Number of Logic Elements / Blocks — 16 LABs (Logic Array Blocks)
Number of Gates — 5,000 typical usable gates
Number of User I/O — 116
Propagation Delay (tpd max) — 10 ns
Maximum Frequency (fmax) — 95.2 MHz
Supply Voltage (VCCINT) — 3.0 V to 3.6 V (3.3 V nominal)
I/O Voltage Support — MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V mixed
Logic Family — CMOS, EEPROM-based
Programming Interface — JTAG (IEEE 1149.1) and IEEE Std. 1532 ISP
Compliance — IEEE Std. 1532 ISP, PCI-compatible I/O
生命周期状态 — Obsolete (per HighqualityPCB listing)

数据手册与资源

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