EPM3256ATI144-10 - MAX 3000A 256-Macrocell 10ns CPLD | Intel
料号： EPM3256ATI144-10 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
EPM3256ATI144-10 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between small discrete logic gates (74-series) and large FPGAs in the programmable logic hierarchy. It provides predictable timing, instant-on operation from on-chip EEPROM, and is well suited to glue logic, bus interface, and state-machine functions. The MAX 3000A family uses a classic MAX architecture with 16 Logic Array Blocks (LABs), each containing 16 macrocells interconnected by a programmable interconnect array (PIA).
Key features include 3.3V in-system programmability (ISP) compliant with IEEE Std. 1532, MultiVolt I/O supporting 1.8V/2.5V/3.3V/5.0V mixed-voltage interfacing, 5,000 typical usable gates, 116 user I/O pins, and a maximum toggle frequency of 95.2 MHz. The device operates from a single 3.0V to 3.6V supply with industrial temperature range of -40°C to +85°C. PCI-compatible I/O drive and programmable slew-rate control make it suitable for board-level bus applications.
The EPM3256ATI144-10 leverages EEPROM-based configuration cells for instant-on behavior with no external boot memory required, predictable deterministic routing delays that simplify static timing analysis, and JTAG-based IEEE 1149.1 boundary-scan support for board testability. Designers can target the part with the legacy Altera MAX+PLUS II or the modern Quartus II toolchain.
Typical applications include bus-interface bridges, address decoding and glue logic for legacy microcontrollers, peripheral controllers (UART, SPI, I2C bridges), industrial control boards, and PCI add-in card glue logic. Its instant-on, deterministic timing, and 116 I/O make it a versatile choice for medium-complexity logic consolidation.
When designing with this device, ensure JTAG chain integrity (TDI/TDO/TMS/TCK pull-ups per IEEE 1149.1), respect the 3.3V VCCINT tolerance, and use Quartus II 13.0 SP1 or MAX+PLUS II for legacy design flows. Note that new designs should generally migrate to MAX II or MAX V families.
This page synthesizes distributor availability, drop-in same-family alternatives, and practical design notes not consolidated on a single manufacturer page.
直接替换替代料： EPM3256ATI144-10 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM3256ATI144-10 （相同外形与封装尺寸） ——差异在于 Operating Temperature, Package, Propagation Delay (tPD), RoHS Status, JTAG Support.
快速对比工具——选择替代料号进行并排对比：
EPM3256ATC144-10N
✅ 直接替换✓ 有现货
$14.5 / 个
查看数据手册 →EPM3256ATC144-10AA
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$11.6 / 个
查看数据手册 →EPM3256ATC144-10
✅ 直接替换✓ 有现货
$9.75 / 个
查看数据手册 →EPM3256ATC144-7N
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$17.2 / 个
查看数据手册 →EPM3256ATC144-7
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$17.06 / 个
查看数据手册 →EPM3128ATI144-10N
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$10.32 / 个
查看数据手册 →EPM3256ATI144-10 最大额定值与电气特性
| Series | MAX 3000A |
| Programmable Type | In-System Programmable (ISP), EEPROM-based |
| Number of Macrocells | 256 |
| Number of Logic Elements / Blocks | 16 LABs (Logic Array Blocks) |
| Number of Gates | 5,000 typical usable gates |
| Number of User I/O | 116 |
| Propagation Delay (tpd max) | 10 ns |
| Maximum Frequency (fmax) | 95.2 MHz |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) |
| I/O Voltage Support | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V mixed |
| Logic Family | CMOS, EEPROM-based |
| 工作温度 | -40°C to +85°C (industrial) |
| 封装 | 144-pin TQFP (20x20 mm) |
| 安装类型 | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) and IEEE Std. 1532 ISP |
| Compliance | IEEE Std. 1532 ISP, PCI-compatible I/O |
| 生命周期状态 | Obsolete (per HighqualityPCB listing) |
EPM3256ATI144-10 引脚配置
| 引脚 1 | I/O — User I/O pin (Bank 1) |
| 引脚 2 | I/O — User I/O pin (Bank 1) |
| 引脚 3 | I/O — User I/O pin (Bank 1) |
| 引脚 4 | I/O — User I/O pin (Bank 1) |
| 引脚 5 | I/O — User I/O pin (Bank 1) |
| 引脚 6 | I/O — User I/O pin (Bank 1) |
| 引脚 7 | I/O — User I/O pin (Bank 1) |
| 引脚 8 | I/O — User I/O pin (Bank 1) |
| 引脚 9 | I/O — User I/O pin (Bank 1) |
| 引脚 10 | I/O — User I/O pin (Bank 1) |
| 引脚 11 | I/O — User I/O pin (Bank 1) |
| 引脚 12 | I/O — User I/O pin (Bank 1) |
| 引脚 13 | I/O — User I/O pin (Bank 2) |
| 引脚 14 | I/O — User I/O pin (Bank 2) |
| 引脚 15 | I/O — User I/O pin (Bank 2) |
| 引脚 16 | I/O — User I/O pin (Bank 2) |
| 引脚 17 | I/O — User I/O pin (Bank 2) |
| 引脚 18 | I/O — User I/O pin (Bank 2) |
| 引脚 19 | I/O — User I/O pin (Bank 2) |
| 引脚 20 | I/O — User I/O pin (Bank 2) |
| 引脚 21 | GND — Ground |
| 引脚 22 | I/O — User I/O pin (Bank 2) |
| 引脚 23 | I/O — User I/O pin (Bank 2) |
| 引脚 24 | I/O — User I/O pin (Bank 2) |
| 引脚 25 | I/O — User I/O pin (Bank 2) |
| 引脚 26 | I/O — User I/O pin (Bank 2) |
| 引脚 27 | I/O — User I/O pin (Bank 2) |
| 引脚 28 | I/O — User I/O pin (Bank 2) |
| 引脚 29 | I/O — User I/O pin (Bank 2) |
| 引脚 30 | I/O — User I/O pin (Bank 2) |
| 引脚 31 | GND — Ground |
| 引脚 32 | I/O — User I/O pin (Bank 2) |
| 引脚 33 | I/O — User I/O pin (Bank 3) |
| 引脚 34 | I/O — User I/O pin (Bank 3) |
| 引脚 35 | I/O — User I/O pin (Bank 3) |
| 引脚 36 | I/O — User I/O pin (Bank 3) |
| 引脚 37 | I/O — User I/O pin (Bank 3) |
| 引脚 38 | I/O — User I/O pin (Bank 3) |
| 引脚 39 | I/O — User I/O pin (Bank 3) |
| 引脚 40 | I/O — User I/O pin (Bank 3) |
| 引脚 41 | I/O — User I/O pin (Bank 3) |
| 引脚 42 | I/O — User I/O pin (Bank 3) |
| 引脚 43 | GND — Ground |
| 引脚 44 | I/O — User I/O pin (Bank 3) |
| 引脚 45 | I/O — User I/O pin (Bank 3) |
| 引脚 46 | I/O — User I/O pin (Bank 3) |
| 引脚 47 | I/O — User I/O pin (Bank 3) |
| 引脚 48 | I/O — User I/O pin (Bank 3) |
| 引脚 49 | I/O — User I/O pin (Bank 3) |
| 引脚 50 | I/O — User I/O pin (Bank 3) |
| 引脚 51 | I/O — User I/O pin (Bank 3) |
| 引脚 52 | I/O — User I/O pin (Bank 3) |
| 引脚 53 | I/O — User I/O pin (Bank 3) |
| 引脚 54 | I/O — User I/O pin (Bank 3) |
| 引脚 55 | I/O — User I/O pin (Bank 4) |
| 引脚 56 | I/O — User I/O pin (Bank 4) |
| 引脚 57 | I/O — User I/O pin (Bank 4) |
| 引脚 58 | I/O — User I/O pin (Bank 4) |
| 引脚 59 | I/O — User I/O pin (Bank 4) |
| 引脚 60 | I/O — User I/O pin (Bank 4) |
| 引脚 61 | GND — Ground |
| 引脚 62 | I/O — User I/O pin (Bank 4) |
| 引脚 63 | I/O — User I/O pin (Bank 4) |
| 引脚 64 | I/O — User I/O pin (Bank 4) |
| 引脚 65 | I/O — User I/O pin (Bank 4) |
| 引脚 66 | I/O — User I/O pin (Bank 4) |
| 引脚 67 | I/O — User I/O pin (Bank 4) |
| 引脚 68 | I/O — User I/O pin (Bank 4) |
| 引脚 69 | I/O — User I/O pin (Bank 4) |
| 引脚 70 | I/O — User I/O pin (Bank 4) |
| 引脚 71 | I/O — User I/O pin (Bank 4) |
| 引脚 72 | I/O — User I/O pin (Bank 4) |
| 引脚 73 | TDI — JTAG Test Data In (IEEE 1149.1) |
| 引脚 74 | TMS — JTAG Test Mode Select |
| 引脚 75 | TCK — JTAG Test Clock |
| 引脚 76 | GND — Ground |
| 引脚 77 | VCCINT — Core supply 3.3 V (3.0-3.6 V) |
| 引脚 78 | I/O — User I/O pin (Bank 4) |
| 引脚 79 | I/O — User I/O pin (Bank 4) |
| 引脚 80 | I/O — User I/O pin (Bank 4) |
| 引脚 81 | I/O — User I/O pin (Bank 4) |
| 引脚 82 | I/O — User I/O pin (Bank 1) |
| 引脚 83 | I/O — User I/O pin (Bank 1) |
| 引脚 84 | I/O — User I/O pin (Bank 1) |
| 引脚 85 | I/O — User I/O pin (Bank 1) |
| 引脚 86 | I/O — User I/O pin (Bank 1) |
| 引脚 87 | I/O — User I/O pin (Bank 1) |
| 引脚 88 | I/O — User I/O pin (Bank 1) |
| 引脚 89 | I/O — User I/O pin (Bank 1) |
| 引脚 90 | I/O — User I/O pin (Bank 1) |
| 引脚 91 | GND — Ground |
| 引脚 92 | I/O — User I/O pin (Bank 1) |
| 引脚 93 | I/O — User I/O pin (Bank 1) |
| 引脚 94 | I/O — User I/O pin (Bank 1) |
| 引脚 95 | I/O — User I/O pin (Bank 1) |
| 引脚 96 | I/O — User I/O pin (Bank 1) |
| 引脚 97 | I/O — User I/O pin (Bank 1) |
| 引脚 98 | I/O — User I/O pin (Bank 1) |
| 引脚 99 | I/O — User I/O pin (Bank 1) |
| 引脚 100 | I/O — User I/O pin (Bank 1) |
| 引脚 101 | I/O — User I/O pin (Bank 1) |
| 引脚 102 | I/O — User I/O pin (Bank 2) |
| 引脚 103 | I/O — User I/O pin (Bank 2) |
| 引脚 104 | I/O — User I/O pin (Bank 2) |
| 引脚 105 | I/O — User I/O pin (Bank 2) |
| 引脚 106 | I/O — User I/O pin (Bank 2) |
| 引脚 107 | GND — Ground |
| 引脚 108 | I/O — User I/O pin (Bank 2) |
| 引脚 109 | I/O — User I/O pin (Bank 2) |
| 引脚 110 | I/O — User I/O pin (Bank 2) |
| 引脚 111 | I/O — User I/O pin (Bank 2) |
| 引脚 112 | I/O — User I/O pin (Bank 2) |
| 引脚 113 | I/O — User I/O pin (Bank 2) |
| 引脚 114 | I/O — User I/O pin (Bank 2) |
| 引脚 115 | I/O — User I/O pin (Bank 3) |
| 引脚 116 | I/O — User I/O pin (Bank 3) |
| 引脚 117 | I/O — User I/O pin (Bank 3) |
| 引脚 118 | I/O — User I/O pin (Bank 3) |
| 引脚 119 | GND — Ground |
| 引脚 120 | I/O — User I/O pin (Bank 3) |
| 引脚 121 | I/O — User I/O pin (Bank 3) |
| 引脚 122 | I/O — User I/O pin (Bank 3) |
| 引脚 123 | I/O — User I/O pin (Bank 3) |
| 引脚 124 | I/O — User I/O pin (Bank 3) |
| 引脚 125 | I/O — User I/O pin (Bank 3) |
| 引脚 126 | I/O — User I/O pin (Bank 3) |
| 引脚 127 | I/O — User I/O pin (Bank 4) |
| 引脚 128 | I/O — User I/O pin (Bank 4) |
| 引脚 129 | I/O — User I/O pin (Bank 4) |
| 引脚 130 | I/O — User I/O pin (Bank 4) |
| 引脚 131 | I/O — User I/O pin (Bank 4) |
| 引脚 132 | GND — Ground |
| 引脚 133 | I/O — User I/O pin (Bank 4) |
| 引脚 134 | I/O — User I/O pin (Bank 4) |
| 引脚 135 | VCCIO — I/O bank supply voltage |
| 引脚 136 | VCCIO — I/O bank supply voltage |
| 引脚 137 | VCCINT — Core supply 3.3 V |
| 引脚 138 | TDO — JTAG Test Data Out |
| 引脚 139 | GND — Ground |
| 引脚 140 | I/O — User I/O pin (Bank 4) |
| 引脚 141 | I/O — User I/O pin (Bank 4) |
| 引脚 142 | I/O — User I/O pin (Bank 4) |
| 引脚 143 | I/O — User I/O pin (Bank 4) |
| 引脚 144 | I/O — User I/O pin (Bank 4) |
典型应用
EPM3256ATI144-10 适用于 6 应用s: Microcontroller Bus-Interface Glue Logic, Address Decoding and Chip-Select Generation, Peripheral Controllers (UART/SPI/I2C Bridges), State Machine and Sequencer Controllers, PCI Add-in Card Auxiliary Logic, Legacy System Sustainment and Last-Time-Buy.
Microcontroller Bus-Interface Glue Logic
The EPM3256ATI144-10 fits microcontroller bus-interface bridge designs where 256 macrocells and 116 user I/Os are needed to consolidate scattered 74-series logic into a single non-volatile device. With 10 ns tpd and 95.2 MHz fmax it comfortably bridges 33 MHz address/data buses. Its instant-on EEPROM eliminates FPGA boot delays on power-up, ensuring deterministic bus arbitration at reset. Pin count supports wide 32-bit data plus 24-bit address plus control signal decoding on a single device.
推荐
Address Decoding and Chip-Select Generation
The 256 macrocells of the EPM3256ATI144-10 support wide address decoding trees for memory-mapped systems with up to 32-bit address buses, generating dozens of chip-select signals with predictable combinational delay. MultiVolt I/O (1.8/2.5/3.3/5.0 V) lets a single CPLD interface modern 1.8 V memory controllers and legacy 5 V peripherals without external level shifters. JTAG ISP allows last-minute CS map updates during board bring-up.
推荐
Peripheral Controllers (UART/SPI/I2C Bridges)
Industrial control boards use the EPM3256ATI144-10 to implement multi-channel UART, SPI, and I2C controllers with hardware state machines rather than firmware bit-banging. The 116 user I/Os support up to a dozen full-duplex serial channels, and the deterministic 10 ns tpd simplifies worst-case latency analysis. Industrial -40 to +85°C operation suits factory floor equipment. JTAG boundary-scan plus ISP simplifies field firmware upgrades via the IEEE Std. 1532 flow.
推荐
State Machine and Sequencer Controllers
The MAX 3000A architecture is optimized for finite state machines (FSMs) and sequencers, making the EPM3256ATI144-10 ideal for motor-control sequencers, instrumentation state machines, and protocol sequencers. Each of the 256 macrocells holds a registered state bit, supporting FSMs with up to 32 states without logic splitting. EEPROM configuration guarantees deterministic startup, critical for safety sequencing where FPGA boot is unacceptable.
推荐
PCI Add-in Card Auxiliary Logic
The PCI-compatible I/O drivers and 3.3V/5V-tolerant MultiVolt interface make the EPM3256ATI144-10 a traditional choice for legacy PCI add-in cards requiring auxiliary glue logic, EEPROM emulation, or local bus decoding. The 116 I/Os accommodate PCI 32-bit data/address plus auxiliary GPIO. Industrial temperature supports outdoor PCI instrumentation. Designers should pair with PCI bridge ASICs and verify against PCI Local Bus Specification 2.2 timing.
推荐
Legacy System Sustainment and Last-Time-Buy
Many industrial and aerospace programs continue to use the EPM3256ATI144-10 in long-lifecycle systems (factory controllers, medical instrumentation, military-grade boards) where redesign is cost-prohibitive. The industrial -40 to +85°C range and EEPROM-based non-volatile configuration suit 15 to 20 year field deployments. Sustainment teams should secure last-time-buy inventory, identify pin-compatible MAX 3000A variants (EPM3256ATC144-10N) for cross-stock, and qualify modern MAX II replacements where PCB rework is feasible.
推荐
推荐产品汇总
工程参考数据： EPM3256ATI144-10 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM3256ATC144-10N | EPM3256ATC144-10AA | EPM3256ATC144-10 | EPM3256ATC144-7N | EPM3128ATI144-10N |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 144-TQFP (20x20 mm) | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same |
| Number of Macrocells | 256 | 256 | 256 | 256 | 256 | 128 (-50%) |
| Propagation Delay (tpd max) | 10 ns | 10 ns | 10 ns | 10 ns | 7.5 ns (faster) | 10 ns |
| Operating Temperature | -40°C to +85°C (industrial) | 0°C to +70°C (commercial) | 0°C to +70°C (commercial) | 0°C to +70°C (commercial) | 0°C to +70°C (commercial) | -40°C to +85°C (industrial) |
| User I/Os | 116 | 116 | 116 | 116 | 116 | 96 |
| VCCINT Supply | 3.0 to 3.6 V (3.3 V nom) | 3.0 to 3.6 V | 3.0 to 3.6 V | 3.0 to 3.6 V | 3.0 to 3.6 V | 3.0 to 3.6 V |
| Series | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
关键差异点
- Industrial temperature range (-40°C to +85°C) （对比 EPM3256ATC144-10N)
- Highest macrocell count in the 144-TQFP MAX 3000A family （对比 EPM3128ATI144-10N)
- 10 ns propagation delay with full I/O count （对比 EPM3256ATC144-7N)
设计说明
The EPM3256ATI144-10 operates from a single 3.3 V VCCINT supply (3.0 to 3.6 V). Decouple VCCINT and each VCCIO bank with 0.1 µF ceramic capacitors placed within 5 mm of each supply pin, plus a bulk 10 µF tantalum per bank. MultiVolt I/O banks must each have their own VCCIO rail (1.8/2.5/3.3/5.0 V) — do not tie VCCIO banks together if your design uses mixed voltages. IccINT during ISP programming is approximately 50% higher than in user mode; ensure regulator headroom.
The 144-TQFP (20x20 mm) has 0.5 mm pitch leads — use 0.15 mm trace/space design rules with 0.25 mm via drill minimum. Provide a solid ground pour under the device for thermal spreading and signal-integrity. Place JTAG header or test points for TDI/TDO/TMS/TCK near the board edge to simplify ISP programming and boundary-scan test. Add 10 kΩ pull-ups on TDI, TMS, and TCK per IEEE 1149.1 to keep the JTAG TAP controller in known state at power-up.
Do not use I/O pins before JTAG programming finishes — leaving pins floating during ISP can cause bus contention. For unused I/O pins, configure them as outputs driving low (not high-Z) in the Quartus II pin assignment. Do not exceed 24 mA sink current per I/O (per the MAX 3000A datasheet recommendation). For new designs, migrate to MAX II (EPM240T144C5N) or MAX V (5M240ZT100C5N) families — they offer more logic density, lower power, and active production status.
合规信息
Compliance information not present in verified web data. EPM3256ATI144-10 is an obsolete CPLD; RoHS status for this specific part was not found in DigiKey/Mouser/Octopart listings. Check Intel/legacy Altera documentation for original compliance declarations.
