EPM3512AFC256-18 vs EPM3512AFC256-10N 对比

详细并排对比 EPM3512AFC256-18 出自 Altera 和 EPM3512AFC256-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFC256-18 EPM3512AFC256-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $17.20 $43.22
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 16 [DATA_NEEDED: number of LABs]
Maximum User I/O Pins 212 —
Pin-to-Pin Delay (tPD1) 18 ns —
Global Clock Networks 4 —
VCCINT (Core Supply) 3.0 V to 3.6 V (3.3 V typical) 3.3 V
VCCIO (I/O Supply) 2.5 V or 3.3 V (MultiVolt) 3.3 V or 2.5 V
工作温度 [DATA_NEEDED: industrial/commercial grade] —
Programming Technology EEPROM (non-volatile) —
In-System Programming IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) —
封装 256-ball FineLine BGA (FCBGA) 256-ball FBGA (17 mm x 17 mm)
Ball Pitch 1.0 mm —
RoHS 状态 [DATA_NEEDED: not specified in retrieved data] [DATA_NEEDED: RoHS status]
安装类型 Surface Mount Surface Mount (BGA)
Usable Gates — 10000
User I/O Pins — 208
Operating Frequency (fMAX) — [DATA_NEEDED: fMAX MHz]
Pin-to-Pin Delay (tPD) — 10 ns
Setup Time (tSU) — 4.5 ns
Technology — CMOS EEPROM-based, non-volatile
Operating Temperature (Commercial) — 0 C to +70 C
ISP Interface — IEEE Std. 1149.1 JTAG, IEEE Std. 1532
MSL 等级 — [DATA_NEEDED: MSL rating]

数据手册与资源

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