EPM3512AFC256-19 vs EPM3512AFC256-10N 对比

详细并排对比 EPM3512AFC256-19 出自 Altera 和 EPM3512AFC256-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFC256-19 EPM3512AFC256-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $10.85 $43.22
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Usable Gates 10000 10000
Logic Array Blocks (LABs) 16 [DATA_NEEDED: number of LABs]
Maximum Operating Frequency 80 MHz —
Pin-to-Pin Delay (tPD) 7.5 ns 10 ns
Speed Grade -19 —
User I/O Pins 208 208
封装 256-ball FineLine BGA (FC) 256-ball FBGA (17 mm x 17 mm)
Supply Voltage VCCINT 3.3 V —
I/O Supply Voltage VCCIO 2.5 V or 3.3 V (5.0 V tolerant inputs) —
Programming Interface JTAG (IEEE 1149.1) / ISP (IEEE 1532) —
Process Technology 0.30 µm CMOS EEPROM —
工作温度 -40C to +85C (industrial) —
Non-volatile Configuration Yes (EEPROM-based) —
安装类型 Surface Mount Surface Mount (BGA)
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Operating Frequency (fMAX) — [DATA_NEEDED: fMAX MHz]
Setup Time (tSU) — 4.5 ns
VCCINT (Core Supply) — 3.3 V
VCCIO (I/O Supply) — 3.3 V or 2.5 V
Technology — CMOS EEPROM-based, non-volatile
Operating Temperature (Commercial) — 0 C to +70 C
ISP Interface — IEEE Std. 1149.1 JTAG, IEEE Std. 1532
MSL 等级 — [DATA_NEEDED: MSL rating]

数据手册与资源

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