EPM3512AFC256-21 vs EPM3512AFC256-10 对比
详细并排对比 EPM3512AFC256-21 出自 Altera 和 EPM3512AFC256-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM3512AFC256-21 | EPM3512AFC256-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $18.75 | $17.50 |
| Device Family | MAX 3000A | — |
| Logic Elements / Macrocells | 512 macrocells | — |
| Usable Gates | 10,000 | 10,000 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum Operating Frequency | 87 MHz | — |
| 封装 | FBGA-256 (FineLine BGA) | 256-pin FBGA |
| 工作温度 | -40C to +85C (industrial) | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) | — |
| Programmable Pins (max) | [DATA_NEEDED: maximum user I/O pin count] | — |
| Programming Interface | JTAG / IEEE Std. 1532 ISP | — |
| 存储器类型 | Non-volatile EPROM/EEPROM cell array | — |
| 安装类型 | Surface Mount (BGA) | Surface Mount |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 3000A |
| Macrocells | — | 512 |
| Maximum I/O Pins | — | 208 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 87 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5-V tolerant |
| Programmable Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) |
| 工作温度范围 | — | [DATA_NEEDED: industrial/commercial operating temperature range] |
| 引脚数量 | — | 256 |
| Architecture | — | MAX (Multiple Array matriX) EEPROM-based |