EPM3512AFC256-22 vs EPM3512AFC256-20 对比

详细并排对比 EPM3512AFC256-22 出自 Intel 和 EPM3512AFC256-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFC256-22 EPM3512AFC256-20
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $16.10 $9.75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 208 (typical for FC256 package) —
Speed Grade -22 (tPD ~22 ns) -20 (20 ns tPD)
Propagation Delay (tPD) 22 ns —
Supply Voltage VCCINT 3.3 V —
I/O Standards Supported 2.5 V, 3.3 V, 5.0 V (VCCIO selectable) —
In-System Programming IEEE Std. 1532-compliant ISP via JTAG —
Configuration Memory On-chip EEPROM (non-volatile) Internal EEPROM
封装 FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch) 256-ball FBGA (Fine-pitch BGA)
安装类型 Surface Mount (BGA) Surface Mount
工作温度 [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: operating temperature range]
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Typical Usable Gates — 10,000
引脚数量 — 256
Operating Voltage (VCCINT) — 3.3 V (3.0 V to 3.6 V)
I/O Voltage (VCCIO) — 2.5 V or 3.3 V (5.0 V tolerant inputs)
I/O Standards — LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant
Program Memory Type — EEPROM (non-volatile)
In-System Programmability — Yes (JTAG IEEE 1149.1)
JTAG Support — Yes (boundary-scan + ISP)
MSL 等级 — [DATA_NEEDED: MSL moisture sensitivity level]

数据手册与资源

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