EPM3512AFC256-23 vs EPM3512AFC256-20 对比

详细并排对比 EPM3512AFC256-23 出自 Altera 和 EPM3512AFC256-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFC256-23 EPM3512AFC256-20
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $15.75 $9.75
Family MAX 3000A MAX 3000A
Macrocells 512 512
Usable Gates 10,000 —
Logic Array Blocks (LABs) 16 (32 macrocells each) —
Maximum Operating Frequency 178.6 MHz —
Propagation Delay (tPD) 5.5 ns —
Pin-to-Pin Delay 23 ns —
Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (MultiVolt) —
User I/O Pins [DATA_NEEDED: user I/O count for FC256] —
封装 256-ball FineLine BGA (FC256), 17 mm x 17 mm 256-ball FBGA (Fine-pitch BGA)
Programming Interface JTAG (IEEE Std. 1149.1) / ISP —
Process Technology 0.30 µm CMOS EEPROM —
工作温度 [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: operating temperature range]
安装类型 Surface Mount (BGA) Surface Mount
Typical Usable Gates — 10,000
Speed Grade — -20 (20 ns tPD)
引脚数量 — 256
Operating Voltage (VCCINT) — 3.3 V (3.0 V to 3.6 V)
I/O Voltage (VCCIO) — 2.5 V or 3.3 V (5.0 V tolerant inputs)
I/O Standards — LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant
Program Memory Type — EEPROM (non-volatile)
In-System Programmability — Yes (JTAG IEEE 1149.1)
JTAG Support — Yes (boundary-scan + ISP)
RoHS 状态 — [DATA_NEEDED: RoHS compliance status]
MSL 等级 — [DATA_NEEDED: MSL moisture sensitivity level]
Configuration Memory — Internal EEPROM

数据手册与资源

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