EPM3512AFC256-7 vs EPM3512AFC256-7N 对比

详细并排对比 EPM3512AFC256-7 出自 Intel 和 EPM3512AFC256-7N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Intel
EPM3512AFC256-7 EPM3512AFC256-7 - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel

EPM3512AFC256-7 - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel

EPM3512AFC256-7 ⚠ 最后一次采购

规格对比

参数 EPM3512AFC256-7 EPM3512AFC256-7N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $58.40 $61.00
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Logic Array Blocks (LABs) 16 —
User I/O Pins 212 —
Usable Gates 10,000 10,000
Pin-to-Pin Logic Delay 7.5 ns —
Counter Frequency (max) 227.3 MHz —
Supply Voltage - Core (VCCINT) 3.0 V to 3.6 V (3.3 V typ.) —
I/O Voltage (VCCIO) 5.0 V / 3.3 V / 2.5 V (MultiVolt) —
封装 256-ball FineLine BGA (FBGA-256) 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch
Programming EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant) —
工作温度 [DATA_NEEDED: operating temperature grade] 0 C to 70 C (commercial)
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Configuration Memory Non-volatile EEPROM —
Product Type — CPLD (Complex Programmable Logic Device)
User I/Os — 208
Logic Blocks — 16 (32 macrocells each)
Propagation Delay (tPD) — 7.5 ns
Maximum Internal Frequency (fMAX) — 116.3 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V
5V Tolerant I/O — Yes
In-System Programmability — IEEE Std. 1532 compliant
Programming Interface — JTAG (IEEE 1149.1)
Process Technology — CMOS EEPROM, 0.30 um

数据手册与资源

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