EPM3512AFC256C vs EPM3512AFC256-7 对比
详细并排对比 EPM3512AFC256C 出自 Intel 和 EPM3512AFC256-7 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EPM3512AFC256-7 - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel
EPM3512AFC256-7 ⚠ 最后一次采购规格对比
| 参数 | EPM3512AFC256C | EPM3512AFC256-7 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $27.95 | $58.40 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/Os | 208 | — |
| Dedicated Input Pins | 12 | — |
| 封装 | 256-ball FineLine BGA (FC) | 256-ball FineLine BGA (FBGA-256) |
| 工作温度 | 0C to +70C (Commercial) | [DATA_NEEDED: operating temperature grade] |
| Speed Grade | C (per datasheet ordering code) | — |
| Configuration Technology | EEPROM (non-volatile, instant-on) | — |
| Core Voltage | 3.3 V | — |
| I/O Standards Supported | MultiVolt: 5.0 V, 3.3 V, 2.5 V | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| PCI Compliance | PCI SIG Local Bus Specification Revision 2.2 | — |
| Programming | In-system programmable via JTAG | EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant) |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| 安装类型 | Surface Mount | Surface Mount |
| User I/O Pins | — | 212 |
| Usable Gates | — | 10,000 |
| Pin-to-Pin Logic Delay | — | 7.5 ns |
| Counter Frequency (max) | — | 227.3 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typ.) |
| I/O Voltage (VCCIO) | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Configuration Memory | — | Non-volatile EEPROM |