EPM3512AFI256-7N vs EPM3512ATI256-10N 对比

详细并排对比 EPM3512AFI256-7N 出自 Altera 和 EPM3512ATI256-10N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3512AFI256-7N EPM3512AFI256-7N - MAX 3000A CPLD, 512 Macrocells | Intel / Altera

EPM3512AFI256-7N - MAX 3000A CPLD, 512 Macrocells | Intel / Altera

EPM3512AFI256-7N ⚠ 最后一次采购

规格对比

参数 EPM3512AFI256-7N EPM3512ATI256-10N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $27.95 $19.85
Family MAX 3000A MAX 3000A
Device Logic Elements / Macrocells 512 macrocells —
Typical Usable Gates 10,000 gates —
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins [DATA_NEEDED: user I/O count] —
Maximum Operating Frequency (fMAX) 116.3 MHz —
Pin-to-Pin Delay (tPD, speed grade -7) approximately 7.5 ns —
Supply Voltage (VCCINT) 3.3 V —
MultiVolt I/O Levels 2.5 V / 3.3 V / 5 V mixed —
Configuration Memory Non-volatile EEPROM —
Programming Interface IEEE 1149.1 JTAG (in-system programmable) —
封装 256-ball FBGA 256-pin BGA (TI256)
工作温度范围 -40C to +85C (industrial) —
Lead-Free / RoHS Yes ('N' suffix, lead-free) —
Design Software Quartus II (legacy MAX 3000A support) —
Speed Grade -7 -10 (10 ns pin-to-pin delay)
安装类型 Surface Mount (BGA) Surface Mount
Manufacturer — Intel (formerly Altera Corporation)
Device — EPM3512A
Macrocells — 512
Usable Gates — 10,000
Maximum User I/O — 212
工作温度 — -40C to +85C (Industrial)
Core Voltage — 3.3 V
I/O Voltage Support — 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt)
Programming Technology — EEPROM (non-volatile, in-system programmable)
JTAG Support — IEEE Std 1149.1 boundary-scan, 4-pin JTAG
Programmable Security Bit — Yes (design protection)
RoHS 状态 — [DATA_NEEDED: RoHS status]
生命周期状态 — Obsolete / Last Time Buy (per Altera product discontinuation notices)

数据手册与资源

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