EPM3512AQC208-10 vs EPM3512AQC208-3 对比

详细并排对比 EPM3512AQC208-10 出自 Altera 和 EPM3512AQC208-3 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AQC208-10 EPM3512AQC208-3
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $22.10 $27.80
Family MAX 3000A MAX 3000A
Usable Gates 10,000 —
Macrocells 512 512
Logic Array Blocks (LABs) 32 16 (32 macrocells each)
User I/Os 208 —
Propagation Delay (tPD) 7.5 ns —
Maximum Frequency (fCNT) 116.3 MHz —
Supply Voltage (VCCINT) 3.3 V —
Configuration Memory EEPROM (non-volatile) —
In-System Programmability Yes (IEEE Std. 1532) Yes (IEEE Std. 1532 compliant)
JTAG Boundary Scan Yes (IEEE 1149.1) —
PCI Compliance PCI Local Bus Spec Rev. 2.2 (-10 speed grade) —
封装 208-pin PQFP PQFP-208
工作温度 0C to +70 C (commercial) [DATA_NEEDED: industrial/commercial grade range]
RoHS 状态 [DATA_NEEDED: RoHS status not in verified data] [DATA_NEEDED: confirm from datasheet]
Device Type — CPLD (Complex Programmable Logic Device)
Maximum User I/O Pins — 172
Speed Grade — -3
Supply Voltage - Core (VCCINT) — 3.3 V
I/O Bank Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (multiVolt)
Boundary-Scan Test — Yes (IEEE Std. 1149.1 / JTAG)
Program/Erase Cycles — 100 minimum [DATA_NEEDED: exact datasheet figure]
Non-Volatile Configuration — Yes (EEPROM-based)
安装类型 — Surface Mount
MSL 等级 — [DATA_NEEDED: moisture sensitivity level]

数据手册与资源

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