EPM3512AQC208-10S vs EPM3512AQC20810 对比
详细并排对比 EPM3512AQC208-10S 出自 Altera 和 EPM3512AQC20810 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM3512AQC208-10S | EPM3512AQC20810 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.75 | $16.80 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | — |
| Usable Gates | 1750 | — |
| Logic Array Blocks (LABs) | 32 (16 macrocells each) | 16 |
| 封装 | 208-pin FineLine BGA-256 | 208-pin PQFP (PQ208) |
| User I/Os | 208 | 172 |
| Speed Grade | -10 (tPD1 = 7.5 ns) | -10 (tPD = 10 ns) |
| Propagation Delay (tPD1) | 7.5 ns (pin-to-pin) | — |
| Supply Voltage - VCCINT (internal) | 3.3 V | — |
| Supply Voltage - VCCIO (I/O) | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) | — |
| Programming Technology | CMOS EEPROM | — |
| In-System Programmability (ISP) | Yes (IEEE Std. 1149.1 JTAG) | — |
| PCI Compliance | Yes (PCI Local Bus Specification Rev 2.2) | PCI Local Bus Specification Revision 2.2 compliant |
| 工作温度 | 0C to +70C (commercial) | — |
| Boundary-Scan (JTAG) | Yes (1149.1 compliant) | — |
| Program/Erase Endurance | 100 cycles minimum | — |
| Logic Family | CMOS | — |
| Process Technology | EEPROM-based CMOS | 0.30 µm CMOS EEPROM |
| RoHS 状态 | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| Logic Type | — | CPLD (EEPROM-based, non-volatile) |
| Macro Cells | — | 512 |
| Usable Gates (equivalent) | — | 10000 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 132 MHz |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG, 3.3 V ISP) |
| Operating Temperature (commercial) | — | 0 °C to +70 °C |
| Configuration Memory | — | On-chip EEPROM, non-volatile, 100+ cycles, 10+ year retention |