EPM3512AQC208-10S vs EPM3512AQC20810 Comparaison
Comparaison détaillée côte à côte de EPM3512AQC208-10S par Altera et EPM3512AQC20810 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM3512AQC208-10S | EPM3512AQC20810 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $16,80 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | — |
| Usable Gates | 1750 | — |
| Logic Array Blocks (LABs) | 32 (16 macrocells each) | 16 |
| Boîtier | 208-pin FineLine BGA-256 | 208-pin PQFP (PQ208) |
| User I/Os | 208 | 172 |
| Speed Grade | -10 (tPD1 = 7.5 ns) | -10 (tPD = 10 ns) |
| Propagation Delay (tPD1) | 7.5 ns (pin-to-pin) | — |
| Supply Voltage - VCCINT (internal) | 3.3 V | — |
| Supply Voltage - VCCIO (I/O) | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) | — |
| Programming Technology | CMOS EEPROM | — |
| In-System Programmability (ISP) | Yes (IEEE Std. 1149.1 JTAG) | — |
| PCI Compliance | Yes (PCI Local Bus Specification Rev 2.2) | PCI Local Bus Specification Revision 2.2 compliant |
| Température de fonctionnement | 0C to +70C (commercial) | — |
| Boundary-Scan (JTAG) | Yes (1149.1 compliant) | — |
| Program/Erase Endurance | 100 cycles minimum | — |
| Logic Family | CMOS | — |
| Process Technology | EEPROM-based CMOS | 0.30 µm CMOS EEPROM |
| Statut RoHS | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| Logic Type | — | CPLD (EEPROM-based, non-volatile) |
| Macro Cells | — | 512 |
| Usable Gates (equivalent) | — | 10000 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 132 MHz |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG, 3.3 V ISP) |
| Operating Temperature (commercial) | — | 0 °C to +70 °C |
| Configuration Memory | — | On-chip EEPROM, non-volatile, 100+ cycles, 10+ year retention |