EPM3512AQC208-15N vs EPM3512AQC208-3N 对比
详细并排对比 EPM3512AQC208-15N 出自 Altera 和 EPM3512AQC208-3N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM3512AQC208-15N | EPM3512AQC208-3N |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $20.50 | $16.40 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macro Cells | 512 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 172 | — |
| Typical Usable Gates | 12,000 | — |
| Number of Logic Elements | 512 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Operating Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt) | 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant) |
| Programmable I/O Standards | LVTTL, LVCMOS, PCI (with external resistor) | — |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| JTAG Support | Yes (BST/Boundary-Scan Test) | — |
| 封装 | PQFP-208 (QC208) | PQFP-208 |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in retrieved snippets] |
| Macrocells | — | 512 |
| User I/O Pins | — | 172 |
| Macrocells per LAB | — | 32 |
| Pin-to-Pin Logic Delay | — | 3 ns (speed grade -3) |
| Global Clock Setup Time | — | [DATA_NEEDED: actual tSU at 3 ns grade] |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| Programming Technology | — | EEPROM (non-volatile, in-system programmable) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| ISP Compliance | — | IEEE Std. 1532 |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED] |