EPM5032JC vs EPM5064JC 对比
详细并排对比 EPM5032JC 出自 Altera 和 EPM5064JC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5032JC | EPM5064JC |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $13.50 | $7.10 |
| Family | MAX 5000 EPLD | MAX 5000 |
| Macrocells | 32 | 64 |
| Logic Gates | 600 usable gates | — |
| Maximum I/O Pins | 40 | — |
| Propagation Delay (tPD) | [DATA_NEEDED: specific speed grade value] | — |
| Supply Voltage (VCC) | 5 V | 5 V (typical, 4.75 V - 5.25 V range) |
| Input Type | TTL-compatible | — |
| 输出类型 | TTL/CMOS-compatible | — |
| 封装 | PLCC-44 | 68-pin PLCC (JEDEC) |
| 工作温度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature grade] |
| 安装类型 | Surface Mount (J-lead) | Surface Mount (socketed) |
| Programmability | UV-erasable (windowed ceramic) / OTP variants | — |
| Design Software | MAX+PLUS II / Quartus legacy | — |
| JEDEC Standard | JEDEC PLCC-44 footprint | — |
| RoHS 状态 | unknown | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | unknown | [DATA_NEEDED: lead-free status] |
| Device Type | — | EPLD (Erasable PLD) |
| Usable Gates | — | 1,250 (approx.) |
| Logic Array Inputs | — | 36 |
| Logic Array Outputs | — | 64 |
| I/O Logic Level | — | TTL / CMOS compatible |
| Configuration Memory | — | EPROM (UV-erasable window or OTP) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: specific tPD grade value] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fCNT grade value] |
| MSL 等级 | — | [DATA_NEEDED: MSL rating] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus II (legacy device support) |