EPM5032JC vs EPM5064JC 비교
다음의 상세 나란히 비교: EPM5032JC 제조: Altera 및 EPM5064JC 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5032JC | EPM5064JC |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $13.50 | $7.10 |
| Family | MAX 5000 EPLD | MAX 5000 |
| Macrocells | 32 | 64 |
| Logic Gates | 600 usable gates | — |
| Maximum I/O Pins | 40 | — |
| Propagation Delay (tPD) | [DATA_NEEDED: specific speed grade value] | — |
| Supply Voltage (VCC) | 5 V | 5 V (typical, 4.75 V - 5.25 V range) |
| Input Type | TTL-compatible | — |
| 출력 유형 | TTL/CMOS-compatible | — |
| 패키지 | PLCC-44 | 68-pin PLCC (JEDEC) |
| 동작 온도 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature grade] |
| 실장 유형 | Surface Mount (J-lead) | Surface Mount (socketed) |
| Programmability | UV-erasable (windowed ceramic) / OTP variants | — |
| Design Software | MAX+PLUS II / Quartus legacy | — |
| JEDEC Standard | JEDEC PLCC-44 footprint | — |
| RoHS 상태 | unknown | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | unknown | [DATA_NEEDED: lead-free status] |
| Device Type | — | EPLD (Erasable PLD) |
| Usable Gates | — | 1,250 (approx.) |
| Logic Array Inputs | — | 36 |
| Logic Array Outputs | — | 64 |
| I/O Logic Level | — | TTL / CMOS compatible |
| Configuration Memory | — | EPROM (UV-erasable window or OTP) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: specific tPD grade value] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fCNT grade value] |
| MSL 레벨 | — | [DATA_NEEDED: MSL rating] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus II (legacy device support) |