EPM5032LC-20 vs EPM5032PC-15 对比

详细并排对比 EPM5032LC-20 出自 Altera 和 EPM5032PC-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5032LC-20 EPM5032PC-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $8.40 $8.10
Device Family MAX 5000 MAX 5000
Product Type EPLD / CPLD (One-Time Programmable / UV-Erasable) —
Usable Gates 600 gates 600
Macrocells 32 —
Logic Blocks (LABs) 1 —
Speed Grade -20 (20 ns pin-to-pin) 15 (15 ns tPD)
Maximum Frequency 71.4 MHz —
Propagation Delay (tPD) 20 ns 15 ns
Supply Voltage (VCC) 5 V ±5% —
工作温度 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) 0C to +70C (commercial)
Dedicated Inputs 7 7
Bidirectional I/O Pins 16 16
Total Inputs 24 —
Output Functions 16 —
Product Terms per Output 16 —
Programmable Interconnect Programmable Interconnect Array (PIA) —
封装 LCC-28 (Plastic Leaded Chip Carrier, J-lead) 28-pin PDIP (PC suffix = windowed CerDIP)
安装类型 Surface Mount Through-Hole (DIP)
RoHS 状态 [DATA_NEEDED: RoHS status] Non-compliant (CerDIP window, contains Be)
MSL 等级 [DATA_NEEDED: MSL] —
Device Type — EPLD (Erasable PLD)
Macro Cells — 32
Logic Elements / LABs — 1 LAB (4 macrocells per group)
Maximum Internal Frequency — 76.9 MHz (some sources list 83.3 MHz)
Operating Voltage (VCC) — 5 V (typ.)
Technology Node — 0.8 micron CMOS
Configuration Memory — UV-Erasable EPROM
Total Array Inputs — 24
Pin/Package Suffix — PC = Windowed Ceramic DIP
Programming Tool — Altera Logic Programmer + MAX+plus II
Lead-Free — No

数据手册与资源

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