EPM5032LC-25 vs EPM5032LC-20 对比

详细并排对比 EPM5032LC-25 出自 Altera 和 EPM5032LC-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5032LC-25 EPM5032LC-20
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $8.20 $8.40
Device Family MAX 5000 MAX 5000
Architecture PAL-type EPLD (Erasable Programmable Logic Device) —
Technology CMOS, UV-erasable / OTP —
Macrocells 32 32
Product Terms 320 —
Dedicated Inputs 7 7
I/O Pins 16 bidirectional —
Total Inputs 24 (7 dedicated + 16 I/O used as input) 24
Propagation Delay (tPD) 25 ns 20 ns
Maximum Internal Frequency 62.5 MHz —
Supply Voltage (VCC) 5 V ±10% (4.5 V to 5.5 V) 5 V ±5%
I/O Standard 5 V CMOS —
工作温度 0 °C to +70 °C (commercial, "LC" suffix) 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants)
封装 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch LCC-28 (Plastic Leaded Chip Carrier, J-lead)
安装类型 Surface Mount, socket-compatible Surface Mount
Configuration Cell Programmable interconnect array (PIA), OTP / UV-erasable —
RoHS 状态 Not RoHS compliant (legacy Altera product) [DATA_NEEDED: RoHS status]
Product Type — EPLD / CPLD (One-Time Programmable / UV-Erasable)
Usable Gates — 600 gates
Logic Blocks (LABs) — 1
Speed Grade — -20 (20 ns pin-to-pin)
Maximum Frequency — 71.4 MHz
Bidirectional I/O Pins — 16
Output Functions — 16
Product Terms per Output — 16
Programmable Interconnect — Programmable Interconnect Array (PIA)
MSL 等级 — [DATA_NEEDED: MSL]

数据手册与资源

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