EPM5032LC-25 vs EPM5032LC-20 Comparison
Detailed side-by-side comparison of EPM5032LC-25 by Altera and EPM5032LC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032LC-25 | EPM5032LC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Device Family | MAX 5000 | MAX 5000 |
| Architecture | PAL-type EPLD (Erasable Programmable Logic Device) | — |
| Technology | CMOS, UV-erasable / OTP | — |
| Macrocells | 32 | 32 |
| Product Terms | 320 | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 16 bidirectional | — |
| Total Inputs | 24 (7 dedicated + 16 I/O used as input) | 24 |
| Propagation Delay (tPD) | 25 ns | 20 ns |
| Maximum Internal Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V ±10% (4.5 V to 5.5 V) | 5 V ±5% |
| I/O Standard | 5 V CMOS | — |
| Operating Temperature | 0 °C to +70 °C (commercial, "LC" suffix) | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) |
| Package | 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch | LCC-28 (Plastic Leaded Chip Carrier, J-lead) |
| Mounting Type | Surface Mount, socket-compatible | Surface Mount |
| Configuration Cell | Programmable interconnect array (PIA), OTP / UV-erasable | — |
| RoHS Status | Not RoHS compliant (legacy Altera product) | [DATA_NEEDED: RoHS status] |
| Product Type | — | EPLD / CPLD (One-Time Programmable / UV-Erasable) |
| Usable Gates | — | 600 gates |
| Logic Blocks (LABs) | — | 1 |
| Speed Grade | — | -20 (20 ns pin-to-pin) |
| Maximum Frequency | — | 71.4 MHz |
| Bidirectional I/O Pins | — | 16 |
| Output Functions | — | 16 |
| Product Terms per Output | — | 16 |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| MSL Level | — | [DATA_NEEDED: MSL] |