EPM5128LC-1 vs EPM5128JC 对比

详细并排对比 EPM5128LC-1 出自 Altera 和 EPM5128JC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5128LC-1 EPM5128JC
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $8.20 $9.75
Family MAX 5000 —
Logic Elements / Macrocells 128 macrocells —
Number of Usable Gates [DATA_NEEDED: usable gates] —
Dedicated Inputs 7 8
Bidirectional I/O Pins 52 —
Total User I/O 60 (max) —
Propagation Delay (tpd) 30 ns —
Supply Voltage (VCC) 5 V (±10%) 5 V (typical)
Process Technology CMOS EPROM, UV-erasable CMOS EPROM
Programmability UV-erasable / OTP (windowed package) —
Package Type 68-pin J-lead ceramic chip carrier (PLCC windowed) PLCC-68 (JLCC) ceramic, J-leaded
工作温度 0C to +70C (commercial) Commercial 0C to +70C
JTAG Support IEEE 1149.1 boundary-scan —
安装类型 Surface Mount (J-lead PLCC socket compatible) Surface Mount (PLCC socket or solder)
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - legacy part]
Lead-Free [DATA_NEEDED: lead-free status] [DATA_NEEDED: lead-free status]
Product Family — MAX 5000
Device Type — EPLD / CPLD
Macrocell Count — 128
Propagation Delay (tPD) — 35 ns
Logic Elements — Programmable AND/OR/XOR array
引脚数 — 68
User I/O Pins — [DATA_NEEDED: user I/O pin count]
Configuration Memory — UV-erasable EPROM (windowed package)
Programming Interface — Altera MAX+PLUS II / A+PLUS / legacy programmer
Boundary Scan — JTAG IEEE 1149.1 (family feature)

数据手册与资源

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