EPM5130WC-2 vs EPM5130WM883B-2 对比

详细并排对比 EPM5130WC-2 出自 Altera 和 EPM5130WM883B-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5130WC-2 EPM5130WM883B-2
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $62.00 $52.00
Device Family MAX 5000 —
Product Type UV-Erasable PLD (CPLD) —
Macrocell Count 128 —
Propagation Delay (tPD) 45 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V —
工作温度 0 °C to 70 °C (Commercial) [DATA_NEEDED: military temperature range]
Process Technology CMOS CMOS
Dedicated Inputs 19 19
User I/O Lines 48 —
Total Inputs (I/O + dedicated) 68 —
Package Type 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing —
Terminal Pitch 0.650 mm —
安装类型 Surface Mount —
Configuration Memory UV-erasable CMOS EEPROM cells —
Speed Grade -2 (45 ns) —
RoHS 状态 [DATA_NEEDED: RoHS status] unknown
Lead-Free [DATA_NEEDED: lead-free status] —
Logic Elements AND/OR array with programmable macrocell register —
Family — MAX 5000
Device Type — UV PLD (UV-erasable programmable logic device)
Macrocells — 128
Logic Array Blocks (LABs) — 8
Propagation Delay (tPD, -2 grade) — 45 ns
Propagation Delay (tPD, -1 grade) — 55 ns (EPM5130WM883B base)
User I/O Pins — 48
Total Inputs — 68
Total Outputs — 48
Interconnect — Programmable Interconnect Array (PIA) - 8 LAB channels
External Clock Inputs — 1
Programming Method — UV-erasable (windowed package)
Development Tool — MAX+PLUS II
Military Processing — MIL-STD-883 Class B (883B suffix)
封装 — [DATA_NEEDED: exact package code]

数据手册与资源

浏览全部产品 创建 BOM 获取报价