EPM5192AJC-25 vs EPM5192AGC 对比

详细并排对比 EPM5192AJC-25 出自 Altera 和 EPM5192AGC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192AJC-25 EPM5192AGC
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $8.20 $56.00
Family MAX 5000 EPLD MAX 5000 (High-Speed, High-Density MAX 5000 Devices)
Manufacturer Altera (now Intel PSG) —
Macrocells 192 192
Propagation Delay (tPD) 25 ns —
封装 PLCC-68 (windowed ceramic, AJC) 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless)
引脚数量 68 —
安装类型 Surface Mount Through-hole (Pin Grid Array)
电源电压 5 V (typical) [DATA_NEEDED: VCC nominal and tolerance]
Logic Blocks MAX 5000 LABs (Logic Array Blocks) —
Programmable Pins [DATA_NEEDED: number of user I/O pins] —
工作温度 [DATA_NEEDED: exact operating temperature range] [DATA_NEEDED: operating temperature range]
Erasure Method UV-erasable (windowed ceramic package) —
Programming Technology EPROM (non-volatile) —
RoHS 状态 [DATA_NEEDED: RoHS compliance status] Non-compliant (ceramic PGA contains lead; legacy military/industrial grade)
Military Grade Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) —
Device Type — UV-Erasable / OTP Complex PLD (EPLD)
Logic Density — High-density (per MAX 5000 family definition)
Architecture — CMOS, sum-of-products with macrocell output logic
Process Technology — CMOS
Speed Grade Suffix — C (commercial grade; specific pin-to-pin delay varies by base number -15/-20)
Programmability — UV-erasable (windowed package) / One-Time-Programmable (windowless variant)
Security Bit — Programmable security bit (per MAX 5000 family)
Lifecycle — Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs)
Programming Support — MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers

数据手册与资源

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