EPM5192AJC-25 vs EPM5192AGC 비교

다음의 상세 나란히 비교: EPM5192AJC-25 제조: Altera 및 EPM5192AGC 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM5192AJC-25 EPM5192AGC
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $8.20 $56.00
Family MAX 5000 EPLD MAX 5000 (High-Speed, High-Density MAX 5000 Devices)
Manufacturer Altera (now Intel PSG) —
Macrocells 192 192
Propagation Delay (tPD) 25 ns —
패키지 PLCC-68 (windowed ceramic, AJC) 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless)
핀 수 68 —
실장 유형 Surface Mount Through-hole (Pin Grid Array)
공급 전압 5 V (typical) [DATA_NEEDED: VCC nominal and tolerance]
Logic Blocks MAX 5000 LABs (Logic Array Blocks) —
Programmable Pins [DATA_NEEDED: number of user I/O pins] —
동작 온도 [DATA_NEEDED: exact operating temperature range] [DATA_NEEDED: operating temperature range]
Erasure Method UV-erasable (windowed ceramic package) —
Programming Technology EPROM (non-volatile) —
RoHS 상태 [DATA_NEEDED: RoHS compliance status] Non-compliant (ceramic PGA contains lead; legacy military/industrial grade)
Military Grade Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) —
Device Type — UV-Erasable / OTP Complex PLD (EPLD)
Logic Density — High-density (per MAX 5000 family definition)
Architecture — CMOS, sum-of-products with macrocell output logic
Process Technology — CMOS
Speed Grade Suffix — C (commercial grade; specific pin-to-pin delay varies by base number -15/-20)
Programmability — UV-erasable (windowed package) / One-Time-Programmable (windowless variant)
Security Bit — Programmable security bit (per MAX 5000 family)
Lifecycle — Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs)
Programming Support — MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers

데이터시트 & 자료

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