EPM5192AJC84-20 vs EPM5192ALC84-15 对比

详细并排对比 EPM5192AJC84-20 出自 Altera 和 EPM5192ALC84-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192AJC84-20 EPM5192ALC84-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $19.20 $13.20
Family MAX 5000 —
Device Type UV-erasable/OTP Complex PLD (CPLD) CPLD / UV-Erasable / OTP Complex PLD
Macrocells 192 192
Propagation Delay (tpd) 33 ns (speed grade -20) —
最大时钟频率 66.7 MHz —
Supply Voltage (Vcc) 4.75 V to 5.25 V —
Dedicated Inputs 7 7
User I/O Lines 64 —
Process Technology CMOS, UV-erasable EEPROM CMOS (EPROM-based)
封装 84-pin PLCC J-Lead (WQCCJ, J84) 84-pin PLCC (QCCJ, J-bend ceramic)
Operating Temperature Grade Commercial Commercial
安装类型 Surface Mount (J-Lead) —
MSL 等级 [DATA_NEEDED: MSL level] —
RoHS 状态 [DATA_NEEDED: RoHS status] —
Programming Tool Altera MAX+PLUS II / Quartus (legacy) —
Lead-Free / Halogen-Free [DATA_NEEDED: lead-free status] —
Device Family — MAX 5000 (EPM5192)
User I/O Pins — 64
Propagation Delay (tPD) — 15 ns
Propagation Delay (Industry Variant) — 25 ns (per MicrochipUSA listing)
Supply Voltage (VCC) — 4.75 V to 5.25 V (nominal 5 V)
Programmability — UV-erasable window / OTP
Terminal Form — J-BEND
Package Code — QCCJ
Package Shape — SQUARE
Architecture — Programmable Logic Array + Macrocell Registers + PIA interconnect

数据手册与资源

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