EPM5192GC-2 vs EPM5192JC 对比

详细并排对比 EPM5192GC-2 出自 Altera 和 EPM5192JC 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192GC-2 EPM5192JC
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $92.00 $16.40
Family MAX 5000 —
Macrocells 192 192
Logic Array Blocks 16 (LABs of 16 macrocells each) —
Usable I/O Pins [DATA_NEEDED: exact user I/O count for PGA package] —
Propagation Delay (tPD) 12 ns typical (-2 grade) —
Counter Frequency 100 MHz minimum —
Supply Voltage (VCC) 5 V nominal —
Technology CMOS EPROM —
Programmable Technology UV-erasable / one-time programmable —
Programming Toolchain Altera MAX+PLUS II —
Package Type Pin Grid Array (PGA), ceramic —
工作温度 Commercial (0C to +70C) [DATA_NEEDED: commercial / industrial / military grade]
Speed Grade -2 —
RoHS 状态 Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) [DATA_NEEDED: original Altera marking not RoHS]
安装类型 Through-hole (PGA socket) Surface Mount
Product Type — CPLD (Complex Programmable Logic Device)
Series — EPM5192 (Classic / MAX-class)
Logic Array Blocks (LABs) — 12
Interconnect Architecture — Programmable Interconnect Array (PIA)
Process Technology — CMOS EPROM (UV-erasable)
封装 — 68-pin PLCC (JC) windowed ceramic
Programming Method — UV-erase + EPROM programmer
Non-Volatile Configuration — Yes (EPROM cell array)
Logic Family — Classic CPLD (EPM5xxx series)
电源电压 — [DATA_NEEDED: VCC nominal]
Propagation Delay — [DATA_NEEDED: tpd spec by speed grade]

数据手册与资源

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