EPM5192GM-1 vs EPM5192GI84 对比

详细并排对比 EPM5192GM-1 出自 Altera 和 EPM5192GI84 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192GM-1 EPM5192GI84
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $27.80 $19.80
Family MAX 5000 MAX 5000
Logic Cells 192 —
Propagation Delay (tpd) 55 ns —
Process Technology CMOS —
Programmable Element UV-erasable EPROM —
封装 CPGA-84 (Windowed Ceramic PGA) 84-pin PGA (WPGA, square, through-hole, pin/peg terminals)
引脚数量 84 —
电源电压 [DATA_NEEDED: VCC nominal] —
工作温度范围 [DATA_NEEDED: commercial/industrial/military grade] -40 C to +85 C (industrial)
Programmable Macrocells 192 —
User I/O Pins [DATA_NEEDED: user I/O count] —
安装类型 Through-Hole (Pin Grid Array socket) Through-Hole (PGA socket or PCB pin/peg)
RoHS Compliance unknown (legacy ceramic PGA) —
Lead-Free Status unknown —
Programming Interface Altera ByteBlaster / JEDEC bitstream —
Development Tool Altera MAX+PLUS II (legacy) —
Device Type — UV-Erasable / OTP Complex PLD (CPLD)
Macrocells — 192
Logic Array Blocks — [DATA_NEEDED: number of LABs]
Package Code — WPGA
Operating Voltage (VCC) — 5 V (typical)
I/O Logic Compatibility — TTL
Temperature Grade — Industrial
Programmable Flip-Flop Modes — D, T, JK, SR
Programmability — UV-erasable (windowed) / OTP
Programming File Format — JEDEC map via MAX+PLUS II / A+PLUS
Propagation Delay — [DATA_NEEDED: tPD in ns]
Max User I/O Pins — [DATA_NEEDED: usable I/O count for this package]
RoHS 状态 — [DATA_NEEDED: most legacy PGA parts are non-RoHS]
Lead-Free — [DATA_NEEDED: legacy part, likely contains lead]
Number of Terminals — 84
Terminal Form — PIN/PEG
Package Shape — SQUARE

数据手册与资源

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