EPM5192GM-1 vs EPM5192JM 对比

详细并排对比 EPM5192GM-1 出自 Altera 和 EPM5192JM 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192GM-1 EPM5192JM
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $27.80 $171.00
Family MAX 5000 MAX 5000
Logic Cells 192 —
Propagation Delay (tpd) 55 ns —
Process Technology CMOS —
Programmable Element UV-erasable EPROM —
封装 CPGA-84 (Windowed Ceramic PGA) 84-pin Ceramic JLCC with quartz window (J84)
引脚数量 84 —
电源电压 [DATA_NEEDED: VCC nominal] —
工作温度范围 [DATA_NEEDED: commercial/industrial/military grade] -55 C to +125 C (military grade, 'M' suffix)
Programmable Macrocells 192 —
User I/O Pins [DATA_NEEDED: user I/O count] —
安装类型 Through-Hole (Pin Grid Array socket) —
RoHS Compliance unknown (legacy ceramic PGA) —
Lead-Free Status unknown —
Programming Interface Altera ByteBlaster / JEDEC bitstream —
Development Tool Altera MAX+PLUS II (legacy) MAX+PLUS II (legacy Altera toolchain)
Device Type — UV-Erasable Programmable Logic Device (EPLD)
Macrocells — 192
Maximum User I/O — 64
Dedicated Inputs — 7
Total Input Channels — 72
Propagation Delay (tPD) — 55 ns
Supply Voltage (VCC) — 4.5 V to 5.5 V (nominal 5 V)
Technology — CMOS, UV-erasable
Logic Architecture — Shared product-term AND/OR, programmable polarity
Programming Method — UV erase + EPROM programmer, JEDEC map
Compliance — MIL-STD-883 processing available on /883B suffix variants

数据手册与资源

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