EPM5192GM vs EPM5192GC84-1 对比

详细并排对比 EPM5192GM 出自 Altera 和 EPM5192GC84-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192GM EPM5192GC84-1
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $58.00 $14.20
Product Family MAX 5000 —
Device Type UV Erasable Programmable Logic Device (PLD) —
Technology CMOS CMOS (EPROM-cell based)
Number of Macrocells 192 —
Usable Gates 3,750 —
Pin-to-Pin Delay (tPD) 15 ns (fastest speed grade); 55 ns (this part) —
Counter Frequency (fCNT) up to 76.9 MHz —
Propagation Delay (tPD, this part) 55 ns —
封装 CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) 84-pin PGA (Pin Grid Array), WPGA code
安装类型 Through-Hole (PGA) Through-hole (PGA socket)
Erasure Method UV (windowed ceramic package) —
电源电压 [DATA_NEEDED: typical VCC range] —
Maximum User I/O [DATA_NEEDED: exact I/O count for CPGA-84] —
工作温度 [DATA_NEEDED: commercial/industrial/military grade] —
RoHS 状态 Non-compliant (contains lead in ceramic PGA) Compliant (per third-party distributor listing)
Process Node [DATA_NEEDED: CMOS process geometry] —
Programming Interface JTAG-compatible (per MAX 5000 family) —
Family — MAX 5000
Product Type — UV-Erasable/OTP Complex PLD (CPLD)
Macrocells — 192
Propagation Delay (tPD) — 40 ns (speed grade -1)
最大时钟频率 — 50 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V
Dedicated Inputs — 7
User I/O Pins — 64
Total Inputs / Outputs — 72 inputs / 64 outputs
Architecture — Shared input/clock and shared product terms
Temperature Grade — Commercial
Programming Method — UV erasure (quartz window) + EPROM programmer
Logic Element Type — Macrocells with AND/OR array

数据手册与资源

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