EPM5192GM - 192-Cell MAX 5000 UV PLD, 55ns | Altera
料号： EPM5192GM ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $85 | $850.00 |
| 100 | $75 | $7,500.00 |
| 500 | $65 | $32,500.00 |
| 1,000 | $58 | $58,000.00 |
EPM5192GM 概述
The MAX 5000 family occupies the programmable-logic tier of the classical PLD taxonomy (PLD -> SPLD/CPLD -> UV-erasable/Electrically erasable CMOS PLD -> MAX 5000 series). As a UV-erasable SPLD, the EPM5192GM was designed in an era when designers needed non-volatile, reprogrammable logic with predictable timing and deterministic pin-to-pin delays — before CPLDs and FPGAs dominated general-purpose logic integration. The 192 logic cells (macro cells) and AND-OR-I/O architecture give the part a strong logic-to-pin ratio, making it well suited for state machines, address decoding, glue logic and bus interfacing.
Key features include 192 macro cells, a tPD as low as 15 ns, an fCNT counter frequency up to 76.9 MHz, and a maximum of 84 user I/O pins (depending on pinout configuration). The CPGA-84 windowed ceramic package provides rugged mechanical stability and UV erasure through the top window. The device operates from a single 5 V supply and is fabricated on a 0.8 µm CMOS process that is well-characterised for industrial and military environments. According to the Altera MAX 5000 datasheet family document, all MAX 5000 devices share a common JEDEC-standard JTAG-compatible programming interface and pinout topology.
Typical applications of the EPM5192GM include legacy industrial control systems, MIL-STD-883 aerospace and defense designs, prototype PLD-based glue logic, bus-architecture address decoding (e.g., DEC, Intel, Motorola microprocessor glue), TTL/CMOS logic replacement and high-reliability long-lifecycle programs. The UV-erasable windowed package also makes it popular for engineering development where iterative erasure and re-programming are required.
When designing with the EPM5192GM, ensure the design uses 5 V tolerant I/O only — the device does not support 3.3 V mixed-voltage operation. Place 0.1 µF decoupling capacitors near every VCC pin and provide a solid ground plane under the package. For high-speed designs, observe the published tSU and tCO timing budgets, and consider the IOL/IOH drive strength when driving backplanes or bused signals.
直接替换替代料： EPM5192GM ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM5192GM （相同外形与封装尺寸） ——差异在于 Package, Device Type, Mounting Type, Propagation Delay (tPD), Technology.
快速对比工具——选择替代料号进行并排对比：
EPM5192GM883B
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$142 / 个
查看数据手册 →EPM5192GC84-1
✅ 直接替换✓ 有现货
$14.2 / 个
查看数据手册 →EPM5192GC-1
✅ 直接替换✓ 有现货
$17.85 / 个
查看数据手册 →EPM5192GC-2
✅ 直接替换✓ 有现货
$92 / 个
查看数据手册 →EPM5192GM 最大额定值与电气特性
| Product Family | MAX 5000 |
| Device Type | UV Erasable Programmable Logic Device (PLD) |
| Technology | CMOS |
| Number of Macrocells | 192 |
| Usable Gates | 3,750 |
| Pin-to-Pin Delay (tPD) | 15 ns (fastest speed grade); 55 ns (this part) |
| Counter Frequency (fCNT) | up to 76.9 MHz |
| Propagation Delay (tPD, this part) | 55 ns |
| 封装 | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) |
| 安装类型 | Through-Hole (PGA) |
| Erasure Method | UV (windowed ceramic package) |
| RoHS 状态 | Non-compliant (contains lead in ceramic PGA) |
| Programming Interface | JTAG-compatible (per MAX 5000 family) |
EPM5192GM 引脚配置
| 引脚 1 | I/O — User I/O pin (function programmable) |
| 引脚 2 | I/O — User I/O pin (function programmable) |
| 引脚 3 | I/O — User I/O pin (function programmable) |
| 引脚 4 | I/O — User I/O pin (function programmable) |
| 引脚 5 | I/O — User I/O pin (function programmable) |
| 引脚 6 | I/O — User I/O pin (function programmable) |
| 引脚 7 | I/O — User I/O pin (function programmable) |
| 引脚 8 | GND — Ground |
| 引脚 9 | I/O — User I/O pin (function programmable) |
| 引脚 10 | I/O — User I/O pin (function programmable) |
| 引脚 11 | I/O — User I/O pin (function programmable) |
| 引脚 12 | I/O — User I/O pin (function programmable) |
| 引脚 13 | I/O — User I/O pin (function programmable) |
| 引脚 14 | I/O — User I/O pin (function programmable) |
| 引脚 15 | I/O — User I/O pin (function programmable) |
| 引脚 16 | I/O — User I/O pin (function programmable) |
| 引脚 17 | I/O — User I/O pin (function programmable) |
| 引脚 18 | GND — Ground |
| 引脚 19 | I/O — User I/O pin (function programmable) |
| 引脚 20 | I/O — User I/O pin (function programmable) |
| 引脚 21 | I/O — User I/O pin (function programmable) |
| 引脚 22 | I/O — User I/O pin (function programmable) |
| 引脚 23 | I/O — User I/O pin (function programmable) |
| 引脚 24 | I/O — User I/O pin (function programmable) |
| 引脚 25 | I/O — User I/O pin (function programmable) |
| 引脚 26 | I/O — User I/O pin (function programmable) |
| 引脚 27 | I/O — User I/O pin (function programmable) |
| 引脚 28 | GND — Ground |
| 引脚 29 | I/O — User I/O pin (function programmable) |
| 引脚 30 | I/O — User I/O pin (function programmable) |
| 引脚 31 | I/O — User I/O pin (function programmable) |
| 引脚 32 | I/O — User I/O pin (function programmable) |
| 引脚 33 | I/O — User I/O pin (function programmable) |
| 引脚 34 | I/O — User I/O pin (function programmable) |
| 引脚 35 | I/O — User I/O pin (function programmable) |
| 引脚 36 | I/O — User I/O pin (function programmable) |
| 引脚 37 | I/O — User I/O pin (function programmable) |
| 引脚 38 | GND — Ground |
| 引脚 39 | I/O — User I/O pin (function programmable) |
| 引脚 40 | I/O — User I/O pin (function programmable) |
| 引脚 41 | I/O — User I/O pin (function programmable) |
| 引脚 42 | I/O — User I/O pin (function programmable) |
| 引脚 43 | I/O — User I/O pin (function programmable) |
| 引脚 44 | I/O — User I/O pin (function programmable) |
| 引脚 45 | I/O — User I/O pin (function programmable) |
| 引脚 46 | I/O — User I/O pin (function programmable) |
| 引脚 47 | I/O — User I/O pin (function programmable) |
| 引脚 48 | GND — Ground |
| 引脚 49 | I/O — User I/O pin (function programmable) |
| 引脚 50 | I/O — User I/O pin (function programmable) |
| 引脚 51 | I/O — User I/O pin (function programmable) |
| 引脚 52 | I/O — User I/O pin (function programmable) |
| 引脚 53 | I/O — User I/O pin (function programmable) |
| 引脚 54 | I/O — User I/O pin (function programmable) |
| 引脚 55 | I/O — User I/O pin (function programmable) |
| 引脚 56 | I/O — User I/O pin (function programmable) |
| 引脚 57 | I/O — User I/O pin (function programmable) |
| 引脚 58 | GND — Ground |
| 引脚 59 | I/O — User I/O pin (function programmable) |
| 引脚 60 | I/O — User I/O pin (function programmable) |
| 引脚 61 | I/O — User I/O pin (function programmable) |
| 引脚 62 | I/O — User I/O pin (function programmable) |
| 引脚 63 | I/O — User I/O pin (function programmable) |
| 引脚 64 | I/O — User I/O pin (function programmable) |
| 引脚 65 | I/O — User I/O pin (function programmable) |
| 引脚 66 | I/O — User I/O pin (function programmable) |
| 引脚 67 | I/O — User I/O pin (function programmable) |
| 引脚 68 | GND — Ground |
| 引脚 69 | I/O — User I/O pin (function programmable) |
| 引脚 70 | I/O — User I/O pin (function programmable) |
| 引脚 71 | I/O — User I/O pin (function programmable) |
| 引脚 72 | I/O — User I/O pin (function programmable) |
| 引脚 73 | I/O — User I/O pin (function programmable) |
| 引脚 74 | I/O — User I/O pin (function programmable) |
| 引脚 75 | I/O — User I/O pin (function programmable) |
| 引脚 76 | I/O — User I/O pin (function programmable) |
| 引脚 77 | I/O — User I/O pin (function programmable) |
| 引脚 78 | GND — Ground |
| 引脚 79 | I/O — User I/O pin (function programmable) |
| 引脚 80 | I/O — User I/O pin (function programmable) |
| 引脚 81 | I/O — User I/O pin (function programmable) |
| 引脚 82 | I/O — User I/O pin (function programmable) |
| 引脚 83 | I/O — User I/O pin (function programmable) |
| 引脚 84 | I/O — User I/O pin (function programmable) |
典型应用
EPM5192GM 适用于 6 应用s: Legacy Industrial Control Logic, Microprocessor Glue Logic, Military / Aerospace Systems, Prototype Development and Engineering Labs, Bus Address Decoding and Chip Select Generation, State Machine and Sequencing Controllers.
Legacy Industrial Control Logic
The EPM5192GM's 192 macrocells and 3,750 usable gates provide ample capacity for state machines and discrete logic replacement in legacy industrial control systems. With a deterministic 55 ns pin-to-pin delay, the device excels at bus decoding, sequencing, and I/O expansion in PLC backplanes. The MAX 5000 architecture gives predictable timing that many long-lifecycle industrial programs depend on. Designers use the EPM5192GM to consolidate dozens of 74-series TTL/CMOS chips into a single windowed PLD for maintainability, while preserving 5 V I/O compatibility with existing backplane logic.
推荐
Microprocessor Glue Logic
The EPM5192GM was designed for the era of DEC, Intel, and Motorola microprocessor systems, where 'glue logic' — address decoding, wait-state generation, bus arbitration, and interrupt steering — had to be implemented in discrete TTL. The device's 192 macrocells and high pin count comfortably handle full 24- or 32-bit address decoding plus peripheral chip-select generation. Pin-to-pin delays of 55 ns suit 8- and 16-bit bus architectures; faster speed grades (down to 15 ns) handle 32-bit systems. The deterministic timing simplifies worst-case timing analysis for mission-critical embedded systems.
推荐
Military / Aerospace Systems
The EPM5192GM's ceramic windowed PGA package and MIL-STD-883 processing options make it a candidate for military and aerospace applications where hermetic packaging and radiation tolerance are valued. The MAX 5000 family is supported by Altera with 883B variants qualified for MIL-STD-883 Class B screening. The 192-macrocell density is sufficient for avionics interface logic, radar timing, and guidance subsystems that demand deterministic SPLD behavior. Designers favour the device when QML-qualified, hermetic-PGA parts are required by program specifications.
推荐
Prototype Development and Engineering Labs
The UV-erasable windowed ceramic package of the EPM5192GM makes it an ideal device for engineering laboratories where iterative design changes are routine. Engineers can erase the part under a UV lamp in 20-30 minutes and re-program it many times during development. The 192-macrocell capacity accommodates full prototype subsystems, and the MAX 5000 family supports JTAG-compatible programming via Altera's legacy programming tools. Once the design stabilises, the engineer migrates to the OTP ceramic PGA (EPM5192GC) or EEPROM variant (EPM5192GI) for production.
推荐
Bus Address Decoding and Chip Select Generation
The EPM5192GM's 192 macrocells and high I/O count make it ideally suited to bus address decoding and chip-select generation in 16- and 32-bit microprocessor systems. Its deterministic 55 ns tPD provides worst-case timing margins that are easy to verify in datasheet-based static timing analysis. The MAX 5000 architecture supports both active-high and active-low output polarities, with internal feedback that allows registered outputs without external glue logic. Designers use the device to replace PAL/GAL-based decode trees that would otherwise consume board area and power.
推荐
State Machine and Sequencing Controllers
The EPM5192GM is a strong choice for implementing Moore and Mealy state machines in deterministic, hardware-described form. Its 192 macrocells accommodate state machines with 16-32 states plus extensive output decoding, while the high I/O count supports wide control buses. Pin-to-pin delays in the 15-55 ns range are well-matched to industrial sequencing timelines. The MAX 5000 family provides configurable output macrocells that can be registered or combinatorial, with feedback paths suitable for sequential logic. Designers favour the device for fail-safe machine control where predictable timing is essential.
推荐
推荐产品汇总
工程参考数据： EPM5192GM ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM5192GM883B | EPM5192GC84-1 | EPM5192GC-1 | EPM5192GC-2 | EPM5192GI |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | CPGA-84 (windowed) | CPGA-84 (windowed) - same | CPGA-84 (windowed) - same | CPGA-84 (windowed) - same | CPGA-84 (windowed) - same | CPGA-84 (windowed) - same |
| Erasure Method | UV (windowed ceramic) | UV (windowed) | OTP (no window) | OTP (no window) | OTP (no window) | EEPROM |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 192 |
| tPD (ns) | 55 | 55 | 55 | 55 (-1 grade) | 70-75 (-2 grade, slower) | 55 |
| Military Grade (MIL-STD-883) | No (commercial) | Yes (Class B) | No | No | No | No |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Reprogrammability | Yes (UV erase + reprogram) | Yes (UV erase + reprogram) | No (OTP) | No (OTP) | No (OTP) | Yes (in-system EEPROM) |
关键差异点
- UV-erasable windowed ceramic package （对比 EPM5192GC-1)
- Standard commercial (non-883) screening （对比 EPM5192GM883B)
- UV (optical) erasure mechanism （对比 EPM5192GI)
设计说明
The EPM5192GM operates from a single 5 V supply. Place a 0.1 µF ceramic decoupling capacitor near every VCC pin (multiple pins on PGA-84) and a 10 µF bulk capacitor at the board's power entry. Use a low-impedance ground plane; the ceramic PGA package relies on multiple GND pins for return paths. Decoupling inductance must be minimised — the device's 55 ns tPD means internal switching edges can reach MHz-range harmonics.
Use a socket for the EPM5192GM in prototype designs. The CPGA-84 ceramic package is fragile and expensive; a PGA-84 machine-pin socket allows easy removal for UV erasure and re-programming. Ensure the socket has adequate mechanical retention — the ceramic package is heavier than plastic and can vibrate loose in high-shock environments. For production designs, migrate to the EPM5192GC (OTP) or EPM5192GI (EEPROM) variant in the same CPGA-84 footprint.
Do not power the EPM5192GM outside its 5 V ±5% supply range — the device is not 3.3 V tolerant and over-voltage can permanently damage the EEPROM/UV cells. Do not use the part in designs that require 3.3 V I/O interfacing; use a modern MAX II/MAX V CPLD instead. Avoid exposure to UV light sources other than the dedicated eraser — sunlight and fluorescent lamps can erase the device over time.
The ceramic PGA-84 package provides good thermal performance. At room temperature, the EPM5192GM dissipates modest power (~0.5-1 W typical) and does not require a heatsink. In enclosed or high-temperature industrial environments, verify junction temperature by measuring case temperature; the ceramic package simplifies this with a thermocouple.
合规信息
Ceramic PGA package contains lead-bearing solder/termination finish and is RoHS-non-compliant per exemption for military/aerospace. MIL-STD-883 variant (EPM5192GM883B) is qualified for Class B screening.
