EPM5192JC vs EPM5192JC-1 对比

详细并排对比 EPM5192JC 出自 Intel 和 EPM5192JC-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192JC EPM5192JC-1
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $16.40 $22.40
Product Type CPLD (Complex Programmable Logic Device) —
Series EPM5192 (Classic / MAX-class) —
Macrocells 192 192
Logic Array Blocks (LABs) 12 —
Interconnect Architecture Programmable Interconnect Array (PIA) —
Process Technology CMOS EPROM (UV-erasable) —
封装 68-pin PLCC (JC) windowed ceramic —
安装类型 Surface Mount —
Programming Method UV-erase + EPROM programmer —
Non-Volatile Configuration Yes (EPROM cell array) —
Logic Family Classic CPLD (EPM5xxx series) —
工作温度 [DATA_NEEDED: commercial / industrial / military grade] 0 C to +70 C (commercial)
电源电压 [DATA_NEEDED: VCC nominal] —
Propagation Delay [DATA_NEEDED: tpd spec by speed grade] —
RoHS 状态 [DATA_NEEDED: original Altera marking not RoHS] —
Family — MAX 5000
Device Type — CPLD - Complex Programmable Logic Device
Technology — CMOS, UV-Erasable / OTP
Usable Gates — 3750
Propagation Delay (tPD) — 40 ns (speed grade -1)
Maximum Internal Frequency (fMAX) — 62.5 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V
User I/O Pins — 84
Package Type — 84-pin Ceramic Quad Flat Pack (CQFP), windowed
JEDEC Package Code — S-CQCC-J84
Configuration Memory — UV-EPROM (erasable under UV lamp)
Programming Interface — Altera MAX programming interface (parallel, pre-JTAG for this family)
Process — CMOS EPROM
I/O Standard — TTL/CMOS 5 V compatible

数据手册与资源

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