EPM5192JC1 vs EPM5192JC2 对比
详细并排对比 EPM5192JC1 出自 Intel 和 EPM5192JC2 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5192JC1 | EPM5192JC2 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $48.30 | $15.90 |
| Family | MAX 5000 (MAX 5xxx CPLD) | MAX 5000 |
| Manufacturer | Intel (formerly Altera Corporation) | — |
| Macro Cells | 192 | — |
| Usable Gates | 3750 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | — |
| Process Technology | 0.5 µm CMOS, UV-erasable EPROM | CMOS, UV-erasable |
| Propagation Delay (typ) | [DATA_NEEDED: propagation delay in ns] | — |
| I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| 封装 | [DATA_NEEDED: exact package from datasheet] | PLCC-68 (JC) |
| 安装类型 | [DATA_NEEDED: surface mount or through-hole] | Surface Mount (socketable PLCC) |
| 工作温度 | [DATA_NEEDED: operating temp range] | — |
| Programming Interface | JTAG-compatible (Altera MAX 5xxx) | — |
| Logic Blocks (LABs) | 24 (8 macrocells per LAB) | — |
| RoHS 状态 | unknown | — |
| AEC-Q100 | not_applicable | — |
| Lifecycle | Obsolete - last-time-buy stock only at franchised distributors | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| Usable Gates (equivalent) | — | 6000 |
| Maximum User I/O | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs | — | 1 (with shared input/clock capability) |
| 最大时钟频率 | — | 50 MHz |
| Propagation Delay (tPD) | — | 45 ns (speed grade -2) |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Programming | — | Altera Master Programmer / ByteBlaster via JTAG-style interface |