EPM5192JI-2 vs EPM5192JI 对比
详细并排对比 EPM5192JI-2 出自 Altera 和 EPM5192JI 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5192JI-2 | EPM5192JI |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.95 | $9.75 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (UV-erasable CMOS Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Usable Gates | 5000 | — |
| Dedicated Inputs | 12 | 7 |
| Flip-Flops | 192 | — |
| Speed Grade | -2 | — |
| 封装 | JLCC-68 (J-Lead Ceramic) | 84-pin PLCC (windowed, J-suffix ceramic) |
| 工作温度 | 0C to +70C (commercial) | -40 C to +125 C (industrial, I-suffix) |
| Programming Technology | UV-Erasable EPROM | — |
| Architecture | Sum-of-products with Programmable Interconnect Array (PIA) | — |
| 电源电压 | 5 V (typical) | 4.75 V to 5.25 V (nominal 5 V) |
| Process Technology | CMOS EPROM | — |
| 安装类型 | Surface Mount | Surface Mount (PLCC socket recommended for UV erasure) |
| RoHS 状态 | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] |
| 生命周期状态 | Obsolete (legacy Altera MAX 5000 family) | — |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Propagation Delay (tpd) | — | 55 ns |
| Technology | — | CMOS EPROM, UV-erasable |
| Programming Method | — | Altera MAX 5000 programming algorithm (device programmer) |
| Erasure Method | — | UV exposure through windowed package |