EPM5192JM vs EPM5192GM-1 对比

详细并排对比 EPM5192JM 出自 Altera 和 EPM5192GM-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192JM EPM5192GM-1
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $171.00 $27.80
Family MAX 5000 MAX 5000
Device Type UV-Erasable Programmable Logic Device (EPLD) —
Macrocells 192 —
Maximum User I/O 64 —
Dedicated Inputs 7 —
Total Input Channels 72 —
Propagation Delay (tPD) 55 ns —
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) —
Technology CMOS, UV-erasable —
封装 84-pin Ceramic JLCC with quartz window (J84) CPGA-84 (Windowed Ceramic PGA)
工作温度范围 -55 C to +125 C (military grade, 'M' suffix) [DATA_NEEDED: commercial/industrial/military grade]
Logic Architecture Shared product-term AND/OR, programmable polarity —
Programming Method UV erase + EPROM programmer, JEDEC map —
Development Tool MAX+PLUS II (legacy Altera toolchain) Altera MAX+PLUS II (legacy)
Compliance MIL-STD-883 processing available on /883B suffix variants —
Logic Cells — 192
Propagation Delay (tpd) — 55 ns
Process Technology — CMOS
Programmable Element — UV-erasable EPROM
引脚数量 — 84
电源电压 — [DATA_NEEDED: VCC nominal]
Programmable Macrocells — 192
User I/O Pins — [DATA_NEEDED: user I/O count]
安装类型 — Through-Hole (Pin Grid Array socket)
RoHS Compliance — unknown (legacy ceramic PGA)
Lead-Free Status — unknown
Programming Interface — Altera ByteBlaster / JEDEC bitstream

数据手册与资源

浏览全部产品 创建 BOM 获取报价