EPM5192LC-2 vs EPM5192LC-35 对比

详细并排对比 EPM5192LC-2 出自 Altera 和 EPM5192LC-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192LC-2 EPM5192LC-35
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $7.95 $15.25
Family MAX 5000 MAX 5000 CPLD
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 192 —
Logic Array Blocks (LABs) 12 —
User I/O Pins 64 —
Dedicated Input Pins 7 —
External Clock Inputs 1 —
Propagation Delay (tPD) 45 ns (typical, -2 speed grade) —
Maximum Internal Frequency 50 MHz —
Interconnect Programmable Interconnect Array (PIA) —
Process Technology CMOS —
封装 PQCC-84 (PLCC-84, J-lead, surface mount) —
Programming Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) —
工作温度 [DATA_NEEDED: commercial/industrial/military grade] Commercial (0C to +70C) per LC suffix
电源电压 5 V (typical MAX 5000 family) —
RoHS 状态 [DATA_NEEDED: pre-RoHS legacy part — likely non-RoHS] Non-compliant (ceramic hermetic package)
Series — MAX 5000
Logic Elements / Macrocells — 192 macrocells
Pin-to-Pin Delay (tPD) — 35 ns
Speed Grade — -35
Programmable Type — UV-Erasable / OTP (EPROM-based)
Package Type — JLCC (J-Lead Ceramic Chip Carrier)
安装类型 — Surface Mount
Logic Voltage — 5 V TTL-compatible I/O
Programming Method — Altera legacy programmer (EPROM-based)
Architecture — LAB-based with Programmable Interconnect Array (PIA)
I/O Standard — TTL
生命周期状态 — Obsolete - last-time-buy stock only
Datasheet Document — Altera MAX 5000 family datasheet (per alldatasheet.com)

数据手册与资源

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