EPM5192LC-2 vs EPM5192LC-35 Comparison

Detailed side-by-side comparison of EPM5192LC-2 by Altera and EPM5192LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192LC-2 EPM5192LC-35
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $7.95 $15.25
Family MAX 5000 MAX 5000 CPLD
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 192 β€”
Logic Array Blocks (LABs) 12 β€”
User I/O Pins 64 β€”
Dedicated Input Pins 7 β€”
External Clock Inputs 1 β€”
Propagation Delay (tPD) 45 ns (typical, -2 speed grade) β€”
Maximum Internal Frequency 50 MHz β€”
Interconnect Programmable Interconnect Array (PIA) β€”
Process Technology CMOS β€”
Package PQCC-84 (PLCC-84, J-lead, surface mount) β€”
Programming Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) β€”
Operating Temperature [DATA_NEEDED: commercial/industrial/military grade] Commercial (0C to +70C) per LC suffix
Supply Voltage 5 V (typical MAX 5000 family) β€”
RoHS Status [DATA_NEEDED: pre-RoHS legacy part β€” likely non-RoHS] Non-compliant (ceramic hermetic package)
Series β€” MAX 5000
Logic Elements / Macrocells β€” 192 macrocells
Pin-to-Pin Delay (tPD) β€” 35 ns
Speed Grade β€” -35
Programmable Type β€” UV-Erasable / OTP (EPROM-based)
Package Type β€” JLCC (J-Lead Ceramic Chip Carrier)
Mounting Type β€” Surface Mount
Logic Voltage β€” 5 V TTL-compatible I/O
Programming Method β€” Altera legacy programmer (EPROM-based)
Architecture β€” LAB-based with Programmable Interconnect Array (PIA)
I/O Standard β€” TTL
Lifecycle Status β€” Obsolete - last-time-buy stock only
Datasheet Document β€” Altera MAX 5000 family datasheet (per alldatasheet.com)

Datasheets & Resources

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