EPM5192LC-2N vs EPM5192LC 对比
详细并排对比 EPM5192LC-2N 出自 Altera 和 EPM5192LC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5192LC-2N | EPM5192LC |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $11.85 | $28.40 |
| Family | MAX 5000 | MAX 7000S |
| Macrocells | 192 | 192 |
| Flip-Flops | 192 | — |
| Logic Elements | 192 macrocells (PAL/GAL-style AND-OR array) | — |
| Package Type | LC (ceramic J-leaded, windowed UV-erasable package family) | — |
| Speed Grade | -2 (tPD approximately 25 ns) | — |
| Propagation Delay (typical) | 25 ns | — |
| 电源电压 | 5 V (typical) | — |
| Programmability | UV-erasable EPROM cell | — |
| 安装类型 | Surface Mount (LC package) | Surface Mount |
| 工作温度 | Commercial (0C to +70C) - inferred from speed-grade -2 designation | — |
| RoHS 状态 | Compliant (per -N lead-free suffix) | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes (per -N suffix) | — |
| Architecture | Programmable Logic Array (PLA) with global PIA | — |
| Programming Interface | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) | JTAG (ByteBlaster-compatible) |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Global Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 55 ns (typical, commercial) |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Process Technology | — | CMOS, UV-erasable/OTP EPROM configuration |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA), fixed delay |
| Boundary-Scan Support | — | JTAG IEEE 1149.1 |
| Operating Temperature (commercial) | — | 0C to +70C |
| 封装 | — | JLCC-68 (windowed ceramic, LC suffix) |