EPM570GT100C3N vs EPM570GT100I5 对比

详细并排对比 EPM570GT100C3N 出自 Altera 和 EPM570GT100I5 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM570GT100C3N EPM570GT100I5
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 有效
库存状态 有库存 有库存
单价(USD) $12.90 $4.95
Family MAX II —
Series MAX II G (Green) MAX II
Logic Elements 570 —
Macrocells 440 440
User I/O Pins 76 —
User Flash Memory 8 Kbits 8 Kbits
Propagation Delay (tPD max) 5.4 ns —
Core Voltage (VCCINT) 1.71 V to 1.89 V (1.8 V typical) —
I/O Voltage Standards 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) —
Process Technology 0.18 um —
工作温度 0C to 85C (TJ, commercial) -40 C to +100 C (Industrial, "I5")
封装 100-pin TQFP (14x14 mm) 100-pin TQFP (14x14 mm, 0.5 mm pitch)
安装类型 Surface Mount Surface Mount (Gull-wing leads)
Programmable Type In-System Programmable (Flash, non-volatile) —
Programming Interface JTAG (IEEE 1149.1) / ISP —
RoHS 状态 Lead free / RoHS Compliant Compliant
Logic Elements (LE) — 570
Maximum User I/O Pins — 76
Propagation Delay (tPD) — 5.4 ns (typ)
Internal Supply Voltage (VCCINT) — 1.71 V to 1.89 V
User I/O Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt)
Programmability — In-System Programmable (ISP) via JTAG, non-volatile flash
Configuration Time — Instant-On (< 1 ms, no external PROM required)
Typical Active Current — [DATA_NEEDED: typical active ICC]
Speed Grade — GT (fast)
JTAG Support — IEEE 1149.1 boundary scan
Global Clock Networks — 4

数据手册与资源

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