EPM7096QC100-10 vs EPM7096QC100-7 对比

详细并排对比 EPM7096QC100-10 出自 Altera 和 EPM7096QC100-7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7096QC100-7 EPM7096QC100-7 - MAX 7000 CPLD, 96 Macrocells, 7.5ns | Altera

EPM7096QC100-7 - MAX 7000 CPLD, 96 Macrocells, 7.5ns | Altera

EPM7096QC100-7 ⚠ 最后一次采购

规格对比

参数 EPM7096QC100-10 EPM7096QC100-7
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $7.10 $31.00
Family MAX 7000 MAX 7000
Macrocells 96 96
Logic Array Blocks 4 —
User I/O Pins 76 —
Propagation Delay (tPD) 10 ns —
Maximum Operating Frequency 100 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Technology EEPROM-based CMOS —
Programming Interface ByteBlaster / parallel (JTAG ISP on MAX 7000S variants) JTAG (IEEE 1149.1) / ByteBlaster
Boundary Scan IEEE Std. 1149.1 (JTAG) on MAX 7000S —
PCI Compliance Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade) —
工作温度 0 °C to +70 °C (commercial) 0C to +70C (commercial)
封装 100-pin PQFP (R-PQFP-G100, 20×14 mm, 0.65 mm pitch) —
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Series — MAX 7000
Product Type — CPLD (Complex Programmable Logic Device)
Programmable Type — EE PLD (EEPROM-based, in-system programmable)
User I/Os — 76
Logic Elements / Gates — 1800 gates (typical)
Pin-to-Pin Delay (tPD) — 7.5 ns
Maximum Frequency (fMAX) — 125 MHz
Supply Voltage - Internal — 4.75 V to 5.25 V
封装 / 外壳 — 100-BQFP (PQFP-100, 20x14 mm, 0.65 mm pitch)
Supplier Device Package — 100-PQFP (20x14)
Program Memory — EEPROM (non-volatile, in-system programmable)

数据手册与资源

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