EPM7128ELC84-20 vs EPM7128ELC84-12 对比

详细并排对比 EPM7128ELC84-20 出自 Altera 和 EPM7128ELC84-12 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7128ELC84-20 EPM7128ELC84-12
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $24.20 $10.40
Series MAX 7000 —
Device Family EPM7128 (CPLD) —
Number of Macrocells 128 —
Number of Usable Gates 2500 —
Number of User I/Os 68 —
Number of Logic Array Blocks (LABs) 8 —
Propagation Delay (tPD) 20 ns —
Maximum Frequency (fCNT) 62.5 MHz —
Supply Voltage (VCC) 5 V —
Supply Voltage Tolerance 4.75 V to 5.25 V —
Technology CMOS, EEPROM-based (non-volatile) —
Programmable Interface IEEE Std. 1149.1 (JTAG) —
Package Type PLCC-84 (J-Lead, J-bend) —
安装类型 Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket compatible)
工作温度 0C to +70C (commercial) 0C to +70C (commercial)
RoHS 状态 Contains lead (pre-RoHS, SnPb finish) Non-compliant (legacy 5V part, SnPb finish)
Family — MAX 7000 (MAX 7000E series)
Logic Family — CMOS, EEPROM-based
Usable Gates — 2,500
Macrocells — 128
Logic Array Blocks (LABs) — 8
User I/Os — 84
Propagation Delay (tpd1) — 12 ns
Internal Global Clock Frequency — 90.9 MHz
Setup Time — 4.5 ns
Supply Voltage (VCCINT / VCCIO) — 5 V (4.75 V to 5.25 V)
封装 — 84-pin PLCC (J-Lead, QCCJ)
Programming Interface — JTAG (IEEE 1149.1) / ISP
引脚数量 — 84

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