EPM7128SLC84-15 vs EPM7096LC84-15 对比
详细并排对比 EPM7128SLC84-15 出自 Intel 和 EPM7096LC84-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EPM7128SLC84-15 - 128-Macrocell MAX 7000S CPLD, 84-PLCC | Intel / Altera
EPM7128SLC84-15 ⚠ 最后一次采购规格对比
| 参数 | EPM7128SLC84-15 | EPM7096LC84-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $10.40 | $9.85 |
| Family | MAX 7000S | MAX 7000 |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | 1,800 |
| User I/Os | 68 (in 84-PLCC) | — |
| 封装 | 84-Pin PLCC (J-Lead, J84) | — |
| Speed Grade | -15 (15 ns pin-to-pin delay) | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Internal Frequency (fMAX) | 76.9 MHz | — |
| Logic Family / Process | CMOS, 5V, EEPROM | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Standard Support | 5.0 V TTL/CMOS (multi-volt I/O compatible with 3.3V) | — |
| Programming Interface | JTAG (IEEE Std. 1149.1), in-system programmable | IEEE Std. 1149.1 JTAG |
| Configuration Memory | Non-volatile EEPROM (instant-on, no boot PROM) | — |
| 工作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS 状态 | Non-RoHS (legacy 5V part) | [DATA_NEEDED: RoHS compliance status] |
| 安装类型 | Surface Mount / Socketed (PLCC-84 socket) | Surface Mount |
| Series | — | MAX 7000 (second-generation MAX architecture) |
| Macro Cells | — | 96 |
| Logic Array Blocks (LABs) | — | 4 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| User I/O Pins | — | 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programmable Type | — | EE PLD (in-system programmable via JTAG) |
| 封装 / 外壳 | — | 84-PLCC (J-Lead) |
| Supplier Device Package | — | 84-PLCC (29.31 x 29.31 mm) |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Erase/Program Endurance | — | [DATA_NEEDED: erase/program cycle count] |