EPM7128SLC84-15 vs EPM7096LC84-15 Comparison

Detailed side-by-side comparison of EPM7128SLC84-15 by Intel and EPM7096LC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7128SLC84-15 EPM7096LC84-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy Obsolete
Family MAX 7000S MAX 7000
Device Type CPLD - Complex Programmable Logic Device —
Macrocells 128 —
Usable Gates 2,500 1,800
User I/Os 68 (in 84-PLCC) —
Package 84-Pin PLCC (J-Lead, J84) —
Speed Grade -15 (15 ns pin-to-pin delay) —
Propagation Delay (tPD) 15 ns —
Maximum Internal Frequency (fMAX) 76.9 MHz —
Logic Family / Process CMOS, 5V, EEPROM —
Supply Voltage (VCCINT) 5 V —
I/O Standard Support 5.0 V TTL/CMOS (multi-volt I/O compatible with 3.3V) —
Programming Interface JTAG (IEEE Std. 1149.1), in-system programmable IEEE Std. 1149.1 JTAG
Configuration Memory Non-volatile EEPROM (instant-on, no boot PROM) —
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial)
RoHS Status Non-RoHS (legacy 5V part) [DATA_NEEDED: RoHS compliance status]
Mounting Type Surface Mount / Socketed (PLCC-84 socket) Surface Mount
Series — MAX 7000 (second-generation MAX architecture)
Macro Cells — 96
Logic Array Blocks (LABs) — 4
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Maximum Operating Frequency — 76.9 MHz
User I/O Pins — 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split])
Supply Voltage (VCC) — 4.75 V to 5.25 V
Programmable Type — EE PLD (in-system programmable via JTAG)
Package / Case — 84-PLCC (J-Lead)
Supplier Device Package — 84-PLCC (29.31 x 29.31 mm)
Data Retention — [DATA_NEEDED: data retention years]
Erase/Program Endurance — [DATA_NEEDED: erase/program cycle count]

Datasheets & Resources

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