EPM7128SQC100-15 vs EPM7128SQC100-7F 对比

详细并排对比 EPM7128SQC100-15 出自 Altera 和 EPM7128SQC100-7F 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7128SQC100-15 EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 ⚠ 最后一次采购

规格对比

参数 EPM7128SQC100-15 EPM7128SQC100-7F
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $8.20 $9.75
Family MAX 7000 MAX 7000S
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 128 —
Logic Array Blocks (LABs) 4 (16 macrocells each) —
User I/Os 84 —
Pin-to-Pin Delay (tPD) 15 ns 7.5 ns
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX value] —
Typical Gate Count 2,500 gates —
Supply Voltage (VCCINT) 5 V (5% tolerance) 4.75 V to 5.25 V (5 V nominal)
Programming Technology EEPROM (in-system programmable via JTAG) —
JTAG Interface IEEE Std. 1149.1 compliant —
封装 100-pin PQFP (Plastic Quad Flat Pack) 100-pin PQFP (SQC100), surface-mount
工作温度 0C to +70C (Commercial) 0 °C to 70 °C (Commercial)
安装类型 Surface Mount Surface Mount
MSL 等级 3 (168 hours) —
RoHS 状态 Non-compliant (SnPb lead finish - legacy PQFP) [DATA_NEEDED: confirmed from manufacturer]
Logic Elements / Blocks — 8 LABs
Number of Macrocells — 128
Number of Usable Gates — 2,500
Maximum Operating Frequency — 125 MHz
Number of User I/O — 84
Programmable Type — In-System Programmable (ISP), EEPROM
JTAG Boundary-Scan — Yes (IEEE 1149.1 BST)
Open-Drain Output Option — Yes
Lead-Free (Pb-Free) — Yes (matte-tin, '-F' suffix)
存储器类型 — Non-volatile (EEPROM configuration)

数据手册与资源

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