EPM7128STC100-10 vs EPM7128STC100-6 对比
详细并排对比 EPM7128STC100-10 出自 Altera 和 EPM7128STC100-6 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 Obsolete规格对比
| 参数 | EPM7128STC100-10 | EPM7128STC100-6 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $7.10 | $5.20 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | — |
| User I/Os | 84 | — |
| Logic Array Blocks | 8 (16 macrocells per LAB) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family | CMOS | — |
| Supply Voltage (VCCINT) | 5 V | — |
| MultiVolt I/O Voltage | 3.3 V / 5 V | — |
| 封装 | TQFP-100 (C100) | 100-pin TQFP (STC100) |
| 引脚数量 | 100 | — |
| 安装类型 | Surface Mount | Surface Mount |
| Programmability | In-System Programmable (JTAG, IEEE 1149.1), EEPROM | — |
| 工作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance status not in provided data] | — |
| Macrocells | — | 128 |
| Equivalent Gates | — | 2,500 |
| User I/O Pins | — | 84 |
| Pin-to-Pin Delay (tPD) | — | 6 ns |
| Maximum Internal Frequency (fCNT) | — | 147.1 MHz |
| Supply Voltage (VCCINT / VCCIO) | — | 5 V |
| Programming Interface | — | JTAG (IEEE Std. 1149.1) / ISP |
| PCI Compliance | — | 33 MHz PCI Local Bus Rev. 2.2 (-6/-7/-10 grades) |
| Lead Pitch | — | 1.0 mm (TQFP) |
| Lead-Free / RoHS | — | Contains lead (non-RoHS original; -6N variant is lead-free) |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |