EPM7128STC100-15N vs EPM7128SQC100-7N 对比

详细并排对比 EPM7128STC100-15N 出自 Intel 和 EPM7128SQC100-7N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7128STC100-15N EPM7128SQC100-7N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $9.20 $7.10
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 7000S MAX 7000S
Usable Gates 2,500 2,500
Macro Cells 128 —
Logic Array Blocks (LABs) 8 (16 macro cells each) —
Maximum User I/O 84 —
Pin-to-Pin Logic Delay (tPD) 15 ns (-15 speed grade) —
Maximum Internal Frequency 76.9 MHz —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Supply Voltage (VCCIO) 3.3 V or 5 V (per bank) —
Technology CMOS EEPROM, in-system programmable —
封装 100-pin TQFP 100-pin PQFP (QFP-100)
工作温度 0C to +70C (commercial) 0C to +70C (commercial)
JTAG (IEEE 1149.1) Yes - in-system programming —
Output Options Totem-pole or open-drain (per pin) —
Dedicated Inputs 4 global inputs —
RoHS 状态 Non-RoHS (legacy SnPb finish typical) Compliant (lead-free 'N' suffix)
生命周期状态 Obsolete (PDN effective 2017-06-01) —
Device Type — CPLD - Complex Programmable Logic Device
Program Memory Type — EEPROM
Number of Macrocells — 128
Number of Logic Array Blocks — 8
Number of Global Clocks — 2
Product Terms per Macrocell — 32
System Gates — 5,000 (max)
Maximum User I/Os — 84
Pin-to-Pin Delay (tPD) — 7.5 ns
Counter Speed — 175.4 MHz
In-System Programmability — Yes (IEEE 1149.1 JTAG)
Operating Voltage (Core) — 5.0 V
I/O Standard Support — multiVolt (2.5V, 3.3V, 5.0V)
Process Technology — 0.30 µm CMOS EEPROM
Security Bit — Programmable (one per device)

数据手册与资源

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