EPM7160SLI84-10 vs EPM7160SLC84-15 对比

详细并排对比 EPM7160SLI84-10 出自 Intel 和 EPM7160SLC84-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Intel
EPM7160SLI84-10 EPM7160SLI84-10 - MAX 7000S CPLD, 160 Macrocells, 84-PLCC | Intel

EPM7160SLI84-10 - MAX 7000S CPLD, 160 Macrocells, 84-PLCC | Intel

EPM7160SLI84-10 ⚠ 最后一次采购

规格对比

参数 EPM7160SLI84-10 EPM7160SLC84-15
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $0.00 $10.80
Series MAX 7000S —
Family CPLD - Complex Programmable Logic Device MAX 7000
Usable Gates 3,200 3,200
Macrocells 160 160
Logic Elements 160 —
User I/O Pins 64 —
Propagation Delay (tpd) 10 ns —
Internal Counter Frequency 167 MHz —
Operating Frequency (max) 100 MHz —
电源电压 5.0 V —
Technology CMOS, EEPROM-based CMOS, EEPROM configuration
封装 84-pin PLCC (LCC-84) —
安装类型 Surface Mount / Through-Hole (socket) Surface Mount (PLCC socket or direct solder)
工作温度 0C to +70C (Commercial) 0 C to 70 C
Programmability In-System (JTAG IEEE 1149.1) + EEPROM —
MultiVolt I/O Yes (2.5V / 3.3V / 5V) —
I/O Standards LVTTL, LVCMOS, TTL, CMOS —
RoHS 状态 [DATA_NEEDED: RoHS status] Not RoHS compliant (contains lead, SnPb finish typical)
Maximum Propagation Delay — 15 ns
Maximum User I/O Pins — 64
Supply Voltage (VCCINT/VCIO) — 4.75 V to 5.25 V (5 V nominal)
I/O Logic Level — Configurable 3.3 V or 5 V
Package Type — PLCC-84 (PQCC84, JEDEC S-PQCC-J84)
Terminal Pitch — 1.270 mm
Programming Interface — JTAG (IEEE 1149.1) in-system programmable
Lifecycle — Obsolete / last-time-buy (per Altera/Intel PDN)

数据手册与资源

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