EPM7160SQC160-10 vs EPM7160SQC160-7 对比

详细并排对比 EPM7160SQC160-10 出自 Altera 和 EPM7160SQC160-7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7160SQC160-10 EPM7160SQC160-7
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $12.20 $9.75
Family MAX 7000S MAX 7000S
Macro Cells 160 —
Logic Elements / Gates 3,200 usable gates —
User I/Os 104 —
Logic Array Blocks (LABs) 10 10
Maximum Operating Frequency 100 MHz —
Pin-to-Pin Propagation Delay (tPD) 10 ns —
Supply Voltage (VCCINT) 5.0 V 4.75 V to 5.25 V (5.0 V nominal)
I/O Voltage Tolerance 5.0 V —
Programming Technology EEPROM, in-system programmable —
JTAG Support IEEE 1149.1 (boundary-scan + ISP) —
封装 PQFP-160 (SQC160) 160-pin PQFP (BQFP, 28x28 mm)
工作温度 0 C to +70 C (commercial) 0 °C to 70 °C (commercial)
Logic Family CMOS —
安装类型 Surface Mount Surface Mount
Process Technology CMOS, EEPROM-based —
RoHS 状态 unknown Not Compliant (per Arrow listing)
Lead-Free unknown —
Macrocells — 160
Usable System Gates — 3,200
Product Terms per Macrocell — 32
Maximum User I/Os — 104
Global Clocks — 2
Speed Grade — -7 (7.5 ns pin-to-pin)
Maximum Propagation Delay (tPD) — 7.5 ns
Program Memory Type — EEPROM (in-system programmable)
JTAG (IEEE 1149.1) — Yes (ISP via JTAG)
PCI Compliance — PCI Local Bus Specification Revision 2.2
Part Status — Obsolete

数据手册与资源

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