EPM7160STC100-10N vs EPM7160STC100-6N 对比

详细并排对比 EPM7160STC100-10N 出自 Altera 和 EPM7160STC100-6N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7160STC100-10N EPM7160STC100-6N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $15.95 $14.20
Family MAX 7000S MAX 7000S
Macrocells 160 —
User I/Os 84 84
Equivalent Gates 3.2K —
Propagation Delay (tPD) 10 ns 6 ns
Internal Operating Frequency 167 MHz max —
Supply Voltage (VCCINT) 4.75 V to 5.25 V —
I/O Voltage (VCCIO) 3.0 V to 5.25 V (MultiVolt) —
Logic Family CMOS CMOS
Programmable Type In-System Programmable (ISP) via JTAG —
Configuration Memory EEPROM (non-volatile) —
封装 TQFP-100 (1 mm height, plastic) TQFP-100 (T100)
工作温度 0C to +70C (Commercial) 0 °C to +70 °C (Commercial)
安装类型 Surface Mount —
JTAG (IEEE 1149.1) Yes —
PCI Compliance Yes (66 MHz) —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
MSL 等级 [DATA_NEEDED: MSL level] —
Logic Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 160
Gates (typical) — 3,200
Internal Frequency — 149.3 MHz (max)
电源电压 — 5 V
Program Memory Type — EEPROM (non-volatile)
In-System Programmability — Yes (IEEE 1149.1 JTAG)
Package Code — LFQFP, S Gull-Wing
I/O Banks — [DATA_NEEDED: I/O bank count]
Lead-Free — [DATA_NEEDED: lead-free status]

数据手册与资源

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