EPM7160STC100-6N vs EPM7160EQC100-20 对比

详细并排对比 EPM7160STC100-6N 出自 Altera 和 EPM7160EQC100-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM7160EQC100-20 EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP

EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP

EPM7160EQC100-20 ⚠ 最后一次采购

规格对比

参数 EPM7160STC100-6N EPM7160EQC100-20
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $14.20 $17.10
Family MAX 7000S MAX 7000 CPLD
Logic Type CPLD (Complex Programmable Logic Device) —
Macro Cells 160 —
User I/Os 84 —
Gates (typical) 3,200 —
Propagation Delay (tPD) 6 ns —
Internal Frequency 149.3 MHz (max) —
电源电压 5 V —
Program Memory Type EEPROM (non-volatile) —
In-System Programmability Yes (IEEE 1149.1 JTAG) Yes (IEEE 1149.1 JTAG, 4-pin)
封装 TQFP-100 (T100) 100-pin Plastic Quad Flat Pack (PQFP, EQFP, EQC100)
Package Code LFQFP, S Gull-Wing —
工作温度 0 °C to +70 °C (Commercial) 0 °C to +90 °C (commercial)
Logic Family CMOS —
I/O Banks [DATA_NEEDED: I/O bank count] —
RoHS 状态 [DATA_NEEDED: RoHS compliance] Not RoHS compliant (legacy Altera MAX 7000)
Lead-Free [DATA_NEEDED: lead-free status] —
Series — MAX 7000
Architecture — CMOS EEPROM-based, non-volatile
Usable Gates — 3,200
Macrocells — 160
Logic Array Blocks (LABs) — 10
Maximum User I/Os — 84
Pin-to-Pin Propagation Delay (tPD) — 20 ns
Maximum Internal Frequency (fCNT) — 62.5 MHz
Supply Voltage (VCCINT) — 5 V nominal (4.75 V to 5.25 V)
I/O Voltage Support — 3.3 V or 5 V configurable
安装类型 — Surface Mount
Reprogram Cycles (typical) — 100
Logic Elements per Macrocell — 36 product terms (expandable)

数据手册与资源

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